HCPL06XX — High Speed-10 MBit/s Logic Gate Optocouplers
April 2009
HCPL0600, HCPL0601, HCPL0611,
HCPL0637, HCPL0638, HCPL0639
High Speed-10 MBit/s Logic Gate Optocouplers
Single Channel: HCPL0600, HCPL0601, HCPL0611
Dual Channel: HCPL0637, HCPL0638, HCPL0639
Features
■
Compact SO8 package
■
Very high speed-10 MBit/s
■
Superior CMR
■
Logic gate output
■
Strobable output (single channel devices)
■
Wired OR-open collector
■
U.L. recognized (File # E90700)
■
IEC60747-5-2 approved (VDE option)
Description
The HCPL06XX optocouplers consist of an AlGaAS
LED, optically coupled to a very high speed integrated
photo-detector logic gate with a strobable output (single
channel devices). The devices are housed in a compact
small-outline package. This output features an open col-
lector, thereby permitting wired OR outputs. The
HCPL0600, HCPL0601 and HCPL0611 output consists
of bipolar transistors on a bipolar process while the
HCPL0637, HCPL0638, and HCPL0639 output consists
of bipolar transistors on a CMOS process for reduced
power consumption. The coupled parameters are guar-
anteed over the temperature range of -40°C to +85°C.
An internal noise shield provides superior common
mode rejection.
– HCPL0600, HCPL0601, HCPL0611 only
Applications
■
Ground loop elimination
■
LSTTL to TTL, LSTTL or 5-volt CMOS
■
Line receiver, data transmission
■
Data multiplexing
■
Switching power supplies
■
Pulse transformer replacement
■
Computer-peripheral interface
Package Dimensions
0.164 (4.16)
0.144 (3.66)
SEATING PLANE
Pin 1
0.202 (5.13)
0.182 (4.63)
0.019 (0.48)
0.010 (0.25)
0.006 (0.16)
0.143 (3.63)
0.123 (3.13)
0.021 (0.53)
0.011 (0.28)
0.008 (0.20)
0.003 (0.08)
0.050 (1.27)
TYP
0.244 (6.19)
0.224 (5.69)
Lead Coplanarity : 0.004 (0.10) MAX
Note:
All dimensions are in inches (millimeters)
©2006 Fairchild Semiconductor Corporation
HCPL06XX Rev. 1.0.8
www.fairchildsemi.com
HCPL06XX — High Speed-10 MBit/s Logic Gate Optocouplers
N/C 1
8 V
CC
+ 1
V
F1
8 V
CC
+ 2
V
F
7 V
E
_ 2
7 V
01
_
3
6 V
O
_
V
F2
3
6 V
02
N/C 4
5 GND
+ 4
5 GND
Single-channel circuit drawing
(HCPL0600, HCPL0601 and HCPL0611)
Dual-channel circuit drawing
(HCPL0637, HCPL0638 and HCPL0639)
Truth Table
(Positive Logic)
Input
H
L
H
L
H*
L*
Enable
H
H
L
L
NC*
NC*
Output
L
H
H
H
L*
H*
*Dual channel devices or single channel devices with pin 7 not connected.
A 0.1µF bypass capacitor must be connected between pins 8 and 5. (See note 1)
©2006 Fairchild Semiconductor Corporation
HCPL06XX Rev. 1.0.8
www.fairchildsemi.com
2
HCPL06XX — High Speed-10 MBit/s Logic Gate Optocouplers
Absolute Maximum Ratings
(No derating required up to 85°C)
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
T
STG
T
OPR
EMITTER
I
F
V
E
V
R
P
I
DETECTOR
Supply Voltage
V
CC
(1 minute max)
I
O
V
O
P
O
Storage Temperature
Operating Temperature
Parameter
Value
-40 to +125
-40 to +85
Single Channel
Dual Channel
Single Channel
5.5
5.0
Single Channel
Dual Channel
7.0
Single Channel
Dual Channel
50
15
7.0
Single Channel
Dual Channel
85
85
45
50
Units
°C
°C
mA
V
V
mW
DC/Average Forward Input Current
(each channel)
Enable Input Voltage
Not to exceed VCC by more than 500mV
Reverse Input Voltage (each channel)
Power Dissipation
V
mA
V
mW
Output Current (each channel)
Output Voltage (each channel)
Collector Output Power Dissipation
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
I
FL
I
FH
V
CC
V
EL
V
EH
T
A
N
R
L
Parameter
Input Current, Low Level
Input Current, High Level
Supply Voltage, Output
Enable Voltage, Low Level
Enable Voltage, High Level
Operating Temperature
Fan Out (TTL load)
Output Pull-up
Single Channel
Dual Channel
Single Channel only
Single Channel only
Min.
0
*6.3
4.5
0
2.0
-40
Max.
250
15
5.5
0.8
V
CC
+85
8
5
Units
µA
mA
V
V
V
°C
TTL Loads
Ω
330
4K
*6.3mA is a guard banded value which allows for at least 20% CTR degradation. Initial input current threshold value is
5.0mA or less
©2006 Fairchild Semiconductor Corporation
HCPL06XX Rev. 1.0.8
www.fairchildsemi.com
3
HCPL06XX — High Speed-10 MBit/s Logic Gate Optocouplers
Electrical Characteristics
(T
A
= -40°C to +85°C unless otherwise specified.)
Individual Component Characteristics
Symbol
EMITTER
V
F
B
VR
∆
VF/
∆
TA
DETECTOR
I
CCH
I
CCL
I
EL
I
EH
V
EH
V
EL
High Level Supply Current
I
F
= 0mA,
V
CC
= 5.5V
I
F
= 10mA,
V
CC
= 5.5V
V
E
= 0.5 V Single Channel
Dual Channel
V
E
= 0.5 V Single Channel
Dual Channel
Single Channel
Single Channel
Single Channel
Single Channel
2.0
0.8
10
15
13
21
-1.6
-1.6
mA
mA
V
V
mA
mA
Input Forward Voltage
I
F
= 10mA
T
A
= 25°C
Input Reverse Breakdown Voltage
Input Diode Temperature Coefficient
I
R
= 10µA
I
F
= 10mA
5.0
-1.5
1.8
1.75
V
mV/°C
V
Parameter
Test Conditions
Min.
Typ.*
Max.
Unit
Low Level Supply Current
Low Level Enable Current
High Level Enable Current
High Level Enable Voltage
Low Level Enable Voltage
V
CC
= 5.5V, V
E
= 0.5V
V
CC
= 5.5V, V
E
= 2.0V
V
CC
= 5.5V, I
F
= 10mA
V
CC
= 5.5V, I
F
= 10mA
(2)
Switching Characteristics
(T
A
= -40°C to +85°C, V
CC
= 5 V, I
F
= 7.5 mA unless otherwise specified.)
Symbol
T
PLH
T
PHL
AC Characteristics
Propagation Delay Time
to Output High Level
Propagation Delay Time
to Output Low Level
(Fig. 20)
Test Conditions
R
L
= 350
Ω
, C
L
= 15pF
(3)
R
L
= 350
Ω
, C
L
= 15pF
(4)
(Fig. 20)
R
L
= 350
Ω
, C
L
= 15pF (Fig. 20)
T
A
= 25°C
T
A
= 25°C
Device
All
Min.
20
Typ. Max. Unit
75
100
ns
All
25
75
100
ns
|T
PHL
-T
PLH
| Pulse Width Distortion
t
r
t
f
t
ELH
All
Single Ch
Dual Ch
50
35
ns
ns
Output Rise Time (10-90%) R
L
= 350
Ω
, C
L
= 15pF
(5)
(Fig. 20)
Output Fall Time (90-10%)
R
L
= 350
Ω
, C
L
= 15pF
(6)
(Fig. 20)
I
F
= 7.5mA, V
EH
= 3.5V, R
L
= 350
Ω
,
C
L
= 15pF
(7)
(Fig. 21)
I
F
= 7.5mA, V
EH
= 3.5V, R
L
= 350
Ω
,
C
L
= 15 pF
(8)
(Fig. 21)
R
L
= 350
Ω
, T
A
=25°C,
I
F
= 0mA,
V
OH
(Min.) = 2.0 V
(9)
(Fig. 22, 23)
|V
CM
| = 10V
|V
CM
| = 50V
17
12
ns
Single Ch
Dual Ch
5
20
ns
Enable Propagation Delay
Time to Output High Level
Enable Propagation Delay
Time to Output Low Level
Common Mode
Transient Immunity
(at Output High Level)
HCPL0600
HCPL0601
HCPL0611
HCPL0600
HCPL0601
HCPL0611
HCPL0600
HCPL0637
HCPL0601
HCPL0638
5000
t
EHL
20
ns
|CM
H
|
V/µs
|V
CM
| = 1,000V HCPL0611 10,000
HCPL0639 25,000
|CM
H
|
Common Mode
Transient Immunity
(at Output Low Level)
R
L
= 350Ω, T
A
=25°C,
I
F
= 7.5mA,
V
OL
(Max.) = 0.8 V
(10)
(Fig. 22, 23)
|V
CM
| = 10V
|V
CM
| = 50V
HCPL0600
HCPL0637
HCPL0601
HCPL0638
5000
V/µs
|V
CM
| = 1,000V HCPL0611 10,000
HCPL0639 25,000
©2006 Fairchild Semiconductor Corporation
HCPL06XX Rev. 1.0.8
www.fairchildsemi.com
4
HCPL06XX — High Speed-10 MBit/s Logic Gate Optocouplers
Transfer Characteristics
(T
A
= -40°C to +85°C unless otherwise specified.)
Symbol
I
OH
V
OL
I
FT
DC Characteristics
High Level Output Current
Low Level Output Voltage
Input Threshold Current
Test Conditions
V
CC
= 5.5V, V
O
= 5.5 V, I
F
= 250µA,
V
E
= 2.0V
(2)
V
CC
= 5.5V, I
F
= 5mA, V
E
= 2.0V,
I
OL
= 13mA
(2)
V
CC
= 5.5V, V
O
= 0.6V, V
E
= 2.0V,
I
OL
= 13mA
Min.
Typ.*
Max.
100
0.6
5
Unit
µA
V
mA
Isolation Characteristics
(T
A
= -40°C to +85°C unless otherwise specified.)
Symbol
I
I-O
Characteristics
Input-Output
Insulation Leakage Current
Withstand Insulation Test Voltage
Resistance (Input to Output)
Capacitance (Input to Output)
Test Conditions
Relative humidity = 45%,
T
A
= 25°C, t = 5s,
V
I-O
= 3000 VDC
(11)
R
H
< 50%, T
A
= 25°C,
I
I-O
≤
2µA, t = 1 min.
(11)
V
I-O
= 500V
(11)
f=
1MHz
(11)
Min.
Typ.*
Max.
1.0*
Unit
µA
V
ISO
R
I-O
C
I-O
3750
10
12
0.6
V
RMS
Ω
pF
*All typical values are at V
CC
= 5 V, T
A
= 25°C
Notes:
1. The V
CC
supply to each optoisolator must be bypassed by a 0.1µF capacitor or larger. This can be either a ceramic
or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible
to the package V
CC
and GND pins of each device.
2. Enable Input – No pull up resistor required as the device has an internal pull up resistor.
3. t
PLH
– Propagation delay is measured from the 3.75mA level on the HIGH to LOW transition of the input current
pulse to the 1.5V level on the LOW to HIGH transition of the output voltage pulse.
4. t
PHL
– Propagation delay is measured from the 3.75mA level on the LOW to HIGH transition of the input current
pulse to the 1.5V level on the HIGH to LOW transition of the output voltage pulse.
5. t
r
– Rise time is measured from the 90% to the 10% levels on the LOW to HIGH transition of the output pulse.
6. t
f
– Fall time is measured from the 10% to the 90% levels on the HIGH to LOW transition of the output pulse.
7. t
ELH
– Enable input propagation delay is measured from the 1.5V level on the HIGH to LOW transition of the input
voltage pulse to the 1.5V level on the LOW to HIGH transition of the output voltage pulse.
8. t
EHL
– Enable input propagation delay is measured from the 1.5V level on the LOW to HIGH transition of the input
voltage pulse to the 1.5V level on the HIGH to LOW transition of the output voltage pulse.
9. CM
H
– The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the high
state (i.e., V
OUT
> 2.0V). Measured in volts per microsecond (V/µs).
10. CM
L
– The maximum tolerable rate of fall of the common mode voltage to ensure the output will remain in the low
output state (i.e., V
OUT
< 0.8V). Measured in volts per microsecond (V/µs).
11. Device considered a two-terminal device: Pins 1, 2, 3 and 4 shorted together, and Pins 5, 6, 7 and 8 shorted
together.
©2006 Fairchild Semiconductor Corporation
HCPL06XX Rev. 1.0.8
www.fairchildsemi.com
5
