Hitachi Single-Chip Microcomputer
H8S/2238 Series
H8S/2238
HD6432238, HD6432238W
H8S/2238R
HD6432238R
H8S/2236
HD6432236, HD6432236W
H8S/2236R
HD6432236R
H8S/2238F-ZTAT™
HD64F2238, HD64F2238R
Hardware Manual
ADE-602-176A
Rev. 2.0
3/19/00
Hitachi Ltd.
Cautions
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use.
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However, contact Hitachi’s sales office before using the product in an application that
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life support.
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particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
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consider normally foreseeable failure rates or failure modes in semiconductor devices and
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Preface
The H8S/2238 Series is a series of high-performance microcontrollers with a 32-bit H8S/2000
CPU core, and a set of on-chip supporting functions required for system configuration.
The H8S/2000 CPU can execute basic instructions in one state, and is provided with sixteen 16-bit
general registers with a 32-bit internal configuration, and a concise and optimized instruction set.
The CPU can handle a 16-Mbyte linear address space (architecturally 4 Gbytes). Programs based
on the high-level language C can also be run efficiently.
The address space is divided into eight areas. The data bus width and access states can be selected
for each of these areas, and various kinds of memory can be connected fast and easily.
Single-power-supply flash memory (F-ZTAT™*) and mask ROM versions are available,
providing a quick and flexible response to conditions from ramp-up through full-scale volume
production, even for applications with frequently changing specifications.
On-chip supporting functions include a 16-bit timer pulse unit (TPU), 8-bit timer unit (TMR),
watchdog timer (WDT), serial communication interface (SCI), I
2
C bus interface (IIC), A/D
converter, D/A converter, and I/O ports.
In addition, an on-chip data transfer controller (DTC) is provided, enabling high-speed data
transfer without CPU intervention.
Use of the H8S/2238 Series enables compact, high-performance systems to be implemented easily.
This manual describes the hardware of the H8S/2238 Series. Refer to the
H8S/2600 Series and
H8S/2000 Series Programming Manual
for a detailed description of the instruction set.
Note: * F-ZTAT is a trademark of Hitachi, Ltd.
Main Revisions and Additions in this Edition
Page
All
2 to 5
Table 1-1 Overview
Item
Revisions
(See Manual for Details)
Addition of H8S/2236, associated
amendments
CPU, A/D converter, and clock pulse
generator operating frequencies
amended
Pin number 66 (FP-100B)/100
(FP-100B) Flash Memory
Programmer Mode entry amended
CVCC, MD2-MD0, AVCC, and Vref
Name and Function descriptions
amended
• High-speed operation amended
Note on TAS instruction added
Note on TAS instruction added
Note on TAS instruction added
Added
12, 13
Table 1-2 Pin Functions in Each Operating
Mode
Table 1-3 Pin Functions
14, 15, 17
20
36
38
45
63
97 to 99
159
184
187, 188
197
204
221
2.1.1 Features
Table 2-1 Instruction Classification
Table 2-2 Combinations of Instructions and
Addressing Modes
Table 2-3 Instructions Classified by Function
2.10 Usage Note
Table 5-4 Interrupt Sources, Vector Addresses, Amended
and Interrupt Priorities
Figure 7-14 Example of Wait State Insertion
Timing
Table 8-2 DTC Functions
Table 8-4 Interrupt Sources, DTC Vector
Addresses, and Corresponding DTCEs
Table 8-9 Number of States Required for
Each Execution Status
Table 9-1 H8S/2238 Series Port Functions
9.3.2 Register Configuration
(4) Port 3 Open-Drain Control Register
(P3ODR)
Amendment of figure 7-14, Example
of Wait State Insertion Timing
Activation sources amended
Amended
Notation description added
Port 7 amended
Description amended
221
221
366
9.3.3 Pin Functions
Figure 9-3 Differences in Open-Drain Output
Types
Figure 10-56 Contention between Overflow
and Counter Clearing
Description added
Added
Amended
Page
402
Item
12.2.2 Timer Control/Status Register (TCSR)
Revisions
(See Manual for Details)
Amendment of table for bits 2 to 0,
WDT0
Input Clock Select
418
481
487
517
518
519
518, 529,
531
539, 540
541
Table 13-2 SCI Registers
Figure 13-28 Operation when Switching
from SCK Pin Function to Port Pin Function
Table 14-2 Smart Card Interface Registers
Note 3 added
Amended
Note 3 added
Figure 15-1 Block Diagram of I
2
C Bus Interface Amended
Figure 15-2 I
2
C Bus Interface Connections
Table 15-2 Register Configuration
15.2.5 I
2
C Bus Control Register (ICCR)
Amended
DDC switch register added
Bit 7 description amended
Bit 4 description amended
Bit 1 description amended
Added
Description amended
Description amended
Text of [1] to [3] amended
Entirely revised
Amended
Amended
Amended
Added
Amended
Amended
Added
15.2.8 DDC Switch Register (DDCSWR)
15.3.1 I
2
C Bus Data Format
542 to 544 15.3.2 Master Transmit Operation
545
546
549
553
554
556, 557
558
560
15.3.3 Master Receive Operation
Figure 15-8 Example of Master Receive
Mode Operation Timing
Figure 15-11 Example of Slave Transmit
Mode Operation Timing
Figure 15-14 Flowchart for Master Transmit
Mode (Example)
Figure 15-15 Flowchart for Master Receive
Mode (Example)
15.3.10 Initialization of Internal State
Table 15-6 I
2
C Bus Timing (SCL and SDA
Output)
Table 15-8 I
2
C Bus Timing (with Maximum
Influence of t
Sr
/t
Sf
)
• Note on ICDR Read at End of Master
Reception, • Notes on Start Condition Issuance
for Retransmission, and • Notes on I
2
C Bus
Interface Stop Condition Instruction Issuance
565
580
16.1.1 Features
Table 16-4 A/D Conversion Time (Single
Mode)
561 to 563 15.4 Usage Notes
Conversion time amended
Amended
