Hitachi Single-Chip Microcomputer
H8S/2268 Series
H8S/2268 F-ZTAT
Hardware Manual
ADE-602-240
Rev 1.0
04/05/01
Hitachi, Ltd.
Cautions
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patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Hitachi bears no responsibility for problems that may arise with third party’s
rights, including intellectual property rights, in connection with use of the information
contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you
have received the latest product standards or specifications before final design, purchase or
use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.
However, contact Hitachi’s sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi
semiconductor products.
Rev. 1.0, 04/01, Page
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Preface
This LSI is a high-performance microcontroller (MCU) made up of the H8S/2000 CPU with an
internal 32-bit configuration as its core, and the peripheral functions required to configure a
system.
This LSI is equipped with a 16-bit timer pulse unit (TPU), an 8-bit timer (TMR), a watchdog timer
2
(WDT), two types of serial communication interfaces (SCIs), an I C bus interface (IIC), an LCD
controller/driver, a DTMF generation circuit, an A/D converter, a D/A converter, and I/O ports as
on-chip peripheral modules for system configuration. In addition, an on-chip data transfer
controller (DTC) is provided, enabling high-speed data transfer without CPU intervention. Use of
this LSI enables compact and high-performance systems to be easily implemented.
A single-power flash memory (F-ZTAT
TM
) version and mask ROM version are available for this
LSI's ROM. The F-ZTAT version provides flexibility as it can be reprogrammed in no time to
cope with all situations from the early stages of mass production to full-scale mass production.
This is particularly applicable to application devices with specifications that will most probably
change.
Note: * F-ZTAT
TM
is a trademark of Hitachi, Ltd.
Target Users: This manual was written for users who will be using the H8S/2268 Series in the
design of application systems. Target users are expected to understand the
fundamentals of electrical circuits, logical circuits, and microcomputers.
Objective:
This manual was written to explain the hardware functions and electrical
characteristics of the H8S/2268 Series to the target users.
Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a
detailed description of the instruction set.
Notes on reading this manual:
•
In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
•
In order to understand the details of the CPU's functions
Read the H8S/2600 Series, H8S/2000 Series Programming Manual.
•
In order to understand the details of a register when its name is known
Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in Appendix A,
Internal I/O Registers.
Rev. 1.0, 04/01, Page
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Examples:
Register name:
The following notation is used for cases when the same or a
similar function, e.g. 16-bit timer pulse unit or serial
communication, is implemented on more than one channel:
XXX_N (XXX is the register name and N is the channel
number)
The MSB is on the left and the LSB is on the right.
Bit order:
Related Manuals:
The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.hitachi.co.jp/Sicd/English/Products/micome.htm
H8S/2268 Series manuals:
Manual Title
H8S/2268 Series Hardware Manual
H8S/2600 Series, H8S/2000 Series Programming Manual
ADE No.
This manual
ADE-602-083
User's manuals for development tools:
Manual Title
C/C++ Compiler, Assembler, Optimized Linkage Editor User's Manual
Simulator Debugger (for UNIX) Users Manual
H8S, H8/300 Series Hitachi Embedded Workshop, Hitachi Debugging
Interface Tutorial
Hitachi Embedded Workshop User's Manual
Hitachi Debugging Interface User's Manual
ADE No.
ADE-702-247
ADE-702-085
ADE-702-231
ADE-702-201
ADE-702-161
Application Notes:
Manual Title
C/C++ Compiler Guide
F-ZTAT Technical Q & A
ADE No.
ADE-702-189
ADE-502-046
Rev. 1.0, 04/01, page
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Contents
Section 1 Overview........................................................................................... 1
1.1
1.2
1.3
1.4
Features .............................................................................................................................1
Internal Block Diagram.....................................................................................................3
Pin Arrangement ...............................................................................................................4
Pin Functions ....................................................................................................................5
Section 2 CPU................................................................................................... 9
2.1
Features .............................................................................................................................9
2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU ..................................10
2.1.2 Differences from H8/300 CPU.............................................................................11
2.1.3 Differences from H8/300H CPU..........................................................................11
CPU Operating Modes ......................................................................................................12
2.2.1 Normal Mode.......................................................................................................12
2.2.2 Advanced Mode ...................................................................................................13
Address Space ...................................................................................................................16
Register Configuration ...................................................................................................... 17
2.4.1 General Registers .................................................................................................18
2.4.2 Program Counter (PC) .........................................................................................19
2.4.3 Extended Control Register (EXR) .......................................................................19
2.4.4 Condition-Code Register (CCR) .......................................................................... 20
2.4.5 Initial Values of CPU Registers ...........................................................................21
Data Formats .....................................................................................................................22
2.5.1 General Register Data Formats ............................................................................22
2.5.2 Memory Data Formats .........................................................................................24
Instruction Set ...................................................................................................................25
2.6.1 Table of Instructions Classified by Function .......................................................26
2.6.2 Basic Instruction Formats ....................................................................................35
Addressing Modes and Effective Address Calculation .....................................................37
2.7.1 Register Direct—Rn.............................................................................................37
2.7.2 Register Indirect—@ERn ....................................................................................37
2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)..............37
2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn ..38
2.7.5 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32....................................38
2.7.6 Immediate—#xx:8, #xx:16, or #xx:32 .................................................................39
2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC)....................................39
2.7.8 Memory Indirect—@@aa:8 ................................................................................39
2.7.9 Effective Address Calculation .............................................................................40
Processing States...............................................................................................................43
Usage Notes ......................................................................................................................45
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2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
