Hitachi Single-Chip Microcomputer
H8/3397 Series
H8/3397
HD6433397
H8/3396
HD6433396
H8/3394
HD6433394
H8/3337 Series
H8/3337Y
HD6473337Y, HD6433337Y
H8/3336Y
HD6433336Y
H8/3334Y
HD6473334Y, HD6433334Y
H8/3334YF-ZTAT™
HD64F3334Y
H8/3337YF-ZTAT™
HD64F3337Y
Hardware Manual
ADE-602-078B
Preface
The H8/3337 Series and H8/3397 Series are series of high-performance microcontrollers with a fast
H8/300 CPU core and a set of on-chip supporting functions optimized for embedded control. These
include ROM, RAM, four types of timers, a serial communication interface, I
2
C bus interface, host
interface, A/D converter, D/A converter, I/O ports, and other functions needed in control system
configurations, so that compact, high-performance systems can be implemented easily. The
H8/3397 Series is a subset of the H8/3337 Series and does not include a host interface and D/A
converter. H8/3337 Series includes the H8/3337Y with 60-kbyte ROM and 2-kbyte RAM, the
H8/3336Y with 48-kbyte ROM and 2-kbyte RAM, and the H8/3334Y with 32-kbyte ROM and
1-kbyte RAM. H8/3397 Series includes the H8/3397 with 60-kbyte ROM and 2-kbyte RAM, the
H8/3396 with 48-kbyte ROM and 2-kbyte RAM, and the H8/3394 with 32-kbyte ROM and 1-kbyte
RAM.
The H8/3337Y, and H8/3334Y are available in mask-ROM versions and in ZTAT™
*1
(zero turn-
around time) versions, providing a quick and flexible response to conditions from ramp-up through
full-scale volume production, even for applications with frequently-changing specifications. In
addition, the H8/3334Y and H8/3337Y have an F-ZTAT™
*2
(flexible-ZTAT) version with on-
board programmability.
This manual describes the hardware of the H8/3337 Series and H8/3397 Series. Refer to the
H8/300
Series Programming Manual
for a detailed description of the instruction set.
Notes: 1. ZTAT is a trademark of Hitachi, Ltd.
2. F-ZTAT is a trademark of Hitachi, Ltd.
Revised Sections and Contents
Page
All
All
Item
H8/3337YF-ZTAT Version added
Explanation of ROM added
Section 18 Mask ROM version/ZTAT version
Section 19 Flash memory 32k-byte version
Section 20 Flash memory 60k-byte version
Table 22-2
Table 22-3
Table 22-4
DC Characteristics (5-V Version)
DC Characteristics (4-V Version)
DC Characteristics (3-V Version)
Revision Contents
493
497
500
507
Values in item “Input capacitance” changed
Values in item “Input capacitance” changed
Values in item “Input capacitance” changed
Values in item “HIF write cycle” changed
Table 22-10 Timing Conditions of On-Chip
Supporting Modules
Contents
Section 1
1.1
1.2
1.3
Overview
.....................................................................................................
Overview ........................................................................................................................
Block Diagram................................................................................................................
Pin Assignments and Functions......................................................................................
1.3.1
Pin Arrangement.............................................................................................
1.3.2
Pin Functions ..................................................................................................
1
1
6
8
8
12
Section 2
2.1
CPU
............................................................................................................... 25
25
25
26
26
27
27
27
28
29
30
31
32
32
34
38
39
41
42
42
44
49
51
52
54
54
55
55
55
56
56
58
2.2
2.3
2.4
2.5
2.6
2.7
Overview ........................................................................................................................
2.1.1
Features...........................................................................................................
2.1.2
Address Space.................................................................................................
2.1.3
Register Configuration....................................................................................
Register Descriptions......................................................................................................
2.2.1
General Registers............................................................................................
2.2.2
Control Registers ............................................................................................
2.2.3
Initial Register Values ....................................................................................
Data Formats...................................................................................................................
2.3.1
Data Formats in General Registers .................................................................
2.3.2
Memory Data Formats....................................................................................
Addressing Modes ..........................................................................................................
2.4.1
Addressing Mode............................................................................................
2.4.2
Calculation of Effective Address....................................................................
Instruction Set.................................................................................................................
2.5.1
Data Transfer Instructions ..............................................................................
2.5.2
Arithmetic Operations ....................................................................................
2.5.3
Logic Operations ............................................................................................
2.5.4
Shift Operations ..............................................................................................
2.5.5
Bit Manipulations ...........................................................................................
2.5.6
Branching Instructions....................................................................................
2.5.7
System Control Instructions ...........................................................................
2.5.8
Block Data Transfer Instruction .....................................................................
CPU States ......................................................................................................................
2.6.1
Overview.........................................................................................................
2.6.2
Program Execution State ................................................................................
2.6.3
Exception-Handling State...............................................................................
2.6.4
Power-Down State ..........................................................................................
Access Timing and Bus Cycle........................................................................................
2.7.1
Access to On-Chip Memory (RAM and ROM) .............................................
2.7.2
Access to On-Chip Supporting Modules and External Devices.....................
Section 3
3.1
MCU Operating Modes and Address Space
..................................... 61
61
61
62
62
64
65
3.2
3.3
3.4
Overview ........................................................................................................................
3.1.1
Mode Selection ...............................................................................................
3.1.2
Mode and System Control Registers .............................................................
System Control Register (SYSCR).................................................................................
Mode Control Register (MDCR) ....................................................................................
Address Space Map in Each Operating Mode................................................................
Section 4
4.1
4.2
Exception Handling
.................................................................................. 69
69
69
69
69
72
72
72
74
78
78
79
84
84
85
4.3
4.4
Overview ........................................................................................................................
Reset
........................................................................................................................
4.2.1
Overview.........................................................................................................
4.2.2
Reset Sequence ...............................................................................................
4.2.3
Disabling of Interrupts after Reset..................................................................
Interrupts ........................................................................................................................
4.3.1
Overview.........................................................................................................
4.3.2
Interrupt-Related Registers.............................................................................
4.3.3
External Interrupts ..........................................................................................
4.3.4
Internal Interrupts ...........................................................................................
4.3.5
Interrupt Handling ..........................................................................................
4.3.6
Interrupt Response Time.................................................................................
4.3.7
Precaution .......................................................................................................
Note on Stack Handling..................................................................................................
Section 5
5.1
Wait-State Controller
............................................................................... 87
87
87
87
88
88
88
88
90
5.2
5.3
Overview ........................................................................................................................
5.1.1
Features...........................................................................................................
5.1.2
Block Diagram................................................................................................
5.1.3
Input/Output Pins............................................................................................
5.1.4
Register Configuration....................................................................................
Register Description .......................................................................................................
5.2.1
Wait-State Control Register (WSCR).............................................................
Wait Modes.....................................................................................................................
Section 6
6.1
Clock Pulse Generator
............................................................................. 93
6.2
6.3
6.4
Overview ........................................................................................................................ 93
6.1.1
Block Diagram................................................................................................ 93
6.1.2
Wait-State Control Register (WSCR)............................................................. 94
Oscillator Circuit ............................................................................................................ 95
Duty Adjustment Circuit................................................................................................. 100
Prescaler ........................................................................................................................ 100
FPGA/CPLD
