Hitachi Single-Chip Microcomputer
H8/3724 Series
HD6433723
HD6433724,HD6473724
HD6433725
HD6433726,HD6473726
H8/3754 Series
HD6433753
HD6433754
Hardware Manual
Preface
The H8/300L Series is a single-chip microcomputer built around the high-speed H8/300L CPU,
and equipped with peripheral system functions on chip. The H8/300L CPU has an instruction set
compatible with the H8/300 CPU, and is ideal for application to realtime control.
The H8/3724 and H8/3754 Series microcomputers are provided with a wide range of peripheral
system functions on chip, including a VFD controller/driver, five timers, a 14-bit PWM, a two-
channel serial communication interface, and an analog-to-digital converter. There are also high-
voltage pins for direct VFD driving, making this chip especially suited to use as a microcontroller
in an embedded system requiring a VFD display.
This manual describes the H8/3724 and H8/3754 Series hardware. Refer to the H8/300L Series
Programming Manual for a detailed description of the instruction set.
Revised Sections and Contents
Page
All
All
1 to 4
18 to 20
54
55
91
92
105
112
185
212
218
332
333
Section
—
—
Overview
Address Space
Notes on Data Access
Notes on Bit Manipulation
ROM overview
Socket Adapter Pin Arrangement
and Memory Map
RAM overview
Notes on Oscillators
14-Bit PWM overview
Bit 5 Chip select output select (CS)
Application Notes
List of Mask Options
Rise Time/Fall Time of High-Voltage
Pins
Revision Contents
Description of H8/3753 and H8/3754 added
“Pull-down MOS” modified to “pull-down
resistor”
Description of H8/3753 and H8/3754 added
Description of H8/3753 and H8/3754 added
Figure modified
Description modified
Description of H8/3753 and H8/3754 added
Description of H8/3753 and H8/3754 added
Description of H8/3753 and H8/3754 added
Section added
Description modified
Description modified
Description added
Description modified including H8/3753 and
H8/3754 addition
Description modified
Contents
Section 1
1.1
1.2
1.3
Overview
.........................................................................................................
Overview.........................................................................................................................
Internal Block Diagram ..................................................................................................
Pin Arrangement and Functions .....................................................................................
1.3.1 Pin Arrangement.................................................................................................
1.3.2 Pin Functions ......................................................................................................
1
1
5
6
6
8
Section 2
2.1
CPU
................................................................................................................... 17
17
17
18
21
22
22
22
24
24
25
26
27
27
29
33
35
37
38
38
40
44
46
47
49
49
50
50
50
51
51
52
2.2
2.3
2.4
2.5
2.6
2.7
Overview.........................................................................................................................
2.1.1 Features...............................................................................................................
2.1.2 Address Space.....................................................................................................
2.1.3 Register Configuration........................................................................................
Register Descriptions......................................................................................................
2.2.1 General Registers................................................................................................
2.2.2 Control Registers ................................................................................................
2.2.3 Initial Register Values.........................................................................................
Data Formats...................................................................................................................
2.3.1 Data Formats in General Registers .....................................................................
2.3.2 Memory Data Formats........................................................................................
Addressing Modes ..........................................................................................................
2.4.1 Addressing Modes ..............................................................................................
2.4.2 Effective Address Calculation ............................................................................
Instruction Set.................................................................................................................
2.5.1 Data Transfer Instructions ..................................................................................
2.5.2 Arithmetic Operations ........................................................................................
2.5.3 Logic Operations ................................................................................................
2.5.4 Shift Operations ..................................................................................................
2.5.5 Bit Manipulations ...............................................................................................
2.5.6 Branching Instructions........................................................................................
2.5.7 System Control Instructions ...............................................................................
2.5.8 Block Data Transfer Instruction .........................................................................
CPU States ......................................................................................................................
2.6.1 Overview.............................................................................................................
2.6.2 Program Execution State ....................................................................................
2.6.3 Program Halt State..............................................................................................
2.6.4 Exception-Handling States .................................................................................
Basic Operation Timing..................................................................................................
2.7.1 Access to On-Chip Memory (RAM, ROM) .......................................................
2.7.2 Access to On-Chip Peripheral Modules .............................................................
2.8
Application Notes ........................................................................................................... 53
2.8.1 Notes on Data Access ......................................................................................... 53
2.8.2 Notes on Bit Manipulation.................................................................................. 55
Section 3
3.1
3.2
System Control
.............................................................................................. 59
59
59
59
60
62
70
71
71
76
76
77
78
79
80
80
86
87
87
89
3.3
3.4
Overview.........................................................................................................................
Exception Handling ........................................................................................................
3.2.1 Reset ...................................................................................................................
3.2.2 Interrupts.............................................................................................................
3.2.3 Interrupt Control Registers .................................................................................
3.2.4 External Interrupts ..............................................................................................
3.2.5 Internal Interrupts ...............................................................................................
3.2.6 Operations When an Interrupt is Raised.............................................................
3.2.7 Return from an Interrupt.....................................................................................
3.2.8 Interrupt Response Time.....................................................................................
3.2.9 Valid Interrupts in Each Mode............................................................................
3.2.10 Notes on Stack Area Use ....................................................................................
System Modes.................................................................................................................
3.3.1 Active Mode .......................................................................................................
3.3.2 Low-Power Operation Mode ..............................................................................
3.3.3 Application Notes ...............................................................................................
System Control Registers ...............................................................................................
3.4.1 System Control Register 1 (SYSCR1)................................................................
3.4.2 System Control Register 2 (SYSCR2)................................................................
Section 4
4.1
4.2
ROM
................................................................................................................. 91
4.3
4.4
4.5
Overview......................................................................................................................... 91
4.1.1 Block Diagram.................................................................................................... 91
PROM Mode................................................................................................................... 92
4.2.1 Setting to PROM Mode ...................................................................................... 92
4.2.2 Socket Adapter Pin Arrangement and Memory Map ......................................... 92
H8/3724ZTAT Programming.......................................................................................... 96
4.3.1 Writing and Verifying ......................................................................................... 96
4.3.2 Precautions When Writing.................................................................................. 99
H8/3726ZTAT Programming.......................................................................................... 100
4.4.1 Writing and Verifying ......................................................................................... 100
4.4.2 Precautions When Writing.................................................................................. 103
Reliability of Written Data ............................................................................................. 104
