Hitachi 16-Bit Single-Chip Microcomputer
H8S/2268 Series,
H8S/2264 Series
H8S/2268
HD6432268, HD6432268W, HD64F2268
H8S/2266
HD6432266, HD6432266W, HD64F2266
H8S/2265
HD6432265, HD6432265W, HD64F2265
H8S/2264
HD6432264, HD6432264W, HD64F2264
H8S/2264R
HD6432264R, HD6432264RW, HD64F2264R
H8S/2262
HD6432262, HD6432262W,
H8S/2262R
HD6432262R, HD6432262RW
ADE-602-240A
Rev 2.0
09/17/02
Hitachi, Ltd.
Hardware Manual
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s
patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Hitachi bears no responsibility for problems that may arise with third party’s
rights, including intellectual property rights, in connection with use of the information
contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you
have received the latest product standards or specifications before final design, purchase or
use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.
However, contact Hitachi’s sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi
semiconductor products.
Rev. 2.0, 09/02, page
ii
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General Precautions on Handling of Product
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass-
through current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note: When power is first supplied, the product’s state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
4. Prohibition of Access to Undefined or Reserved Addresses
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system’s
operation is not guaranteed if they are accessed.
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Configuration of This Manual
This manual comprises the following items:
1. General Precautions on Handling of Product
2. Configuration of This Manual
3. Preface
4. Contents
5. Overview
6. Description of Functional Modules
•
•
CPU and System-Control Modules
On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Main Revisions and Additions in this Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
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Preface
This LSI is a high-performance microcontroller (MCU) made up of the H8S/2000 CPU with an
internal 32-bit configuration as its core, and the peripheral functions required to configure a
system.
A single-power flash memory (F-ZTAT
TM
)* version and a masked-ROM version are available for
this LSI's ROM.
The F-ZTAT version provides flexibility as it can be reprogrammed in no time to
cope with all situations from the early stages of mass production to full-scale mass production.
This is particularly applicable to application devices with specifications that will most probably
change.
List of on-chip peripheral functions:
Series Name
Product Name
PC break controller (PBC)
Data transfer controller (DTC)
16-bit timer pulse unit (TPU)
8-bit timer (TMR_0 to TMR_3)
8-bit reload timer (TMR_4)
Watch dog timer (WDT)
Serial communication interface (SCI)
I C bus interface (IIC)
A/D converter
D/A converter
LCD controller/driver
DTMF generation circuit
Power-on reset circuit
Ports
External interrupts
Interrupt priorities
TM
2
H8S/2268 Series
H8S/2268, 2266, 2265
X2
X1
X3
X4
X4
X2
X3
X 2 (option)
X 10
X2
40 SEG/4 COM
X1
1, 3, 4, 7, 9, F, H, J to N
14
8 levels
H8S/2264 Series
H8S/2264, 2264R, 2262,
2262R
X2
X2
X2
X3
X 1 (option)
X 10
40 SEG/4 COM
X1
1, 3, 4, 7, 9, F, H, J to L
13
Notes: * F-ZTAT
is a trademark of Hitachi, Ltd.
Rev. 2.0, 09/02, page
v
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