HD74AC Series Common Information
September 2000
Customer Service Division
Semiconductor & Integrated Circuits
Hitachi, Ltd.
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FACT Descriptions and Family Characteristics
FACT Descriptions and Family Characteristics
1. Advanced CMOS FACT Logic
FACT logic offers a unique combination of high speed, low power dissipation, high noise immunity, wide
fanout capability, extended power supply range and high reliability.
This data book describes the product line with device specifications as well as material discussing design
considerations and comparing the FACT family to predecessor technologies.
For direct replacement of LS, ALS and other TTL devices, HD74ACT circuits with TTL-type input
thresholds are included in the FACT family. These include the more popular bus drivers/transceivers as
well as many other HD74ACTXXX devices.
1.1 Characteristics
•
Full logic product line
•
Industry standard functions and pinouts for SSI and MSI
•
Meets or exceeds JEDEC standards for HD74ACXX family
•
TTL inputs on selected circuits
•
High performance outputs
Common output structure for standard and buffer drivers
Output Sink/Source Current of 24 mA
Transmission line driving 50
Ω
guaranteed
Operation from 2 to 6 volts guaranteed
Temperature range –40°C to +85°C
Improved ESD protection network
High current latch-up immunity
•
•
•
•
1.2 Interfacing
FACT devices have a wide operating voltage range (V
CC
= 2 to 6 VDC) and sufficient current drive to
interface with most other logic families available today.
Device designators are as follows:
•
HD74AC is a high-speed CMOS device with CMOS input switching levels and buffered CMOS outputs
that can drive
±24
mA of I
OH
and I
OL
current. Industry standard HD74AC nomenclature and pinouts are
used.
•
HD74ACT is a high-speed CMOS device with a TTL-to-CMOS input buffer stage. These device inputs
are designed to interface with TTL outputs operating with a V
CC
= 5 V
±0.5
V with V
OH
= 2.4 V and V
OL
= 0.4 V, but are functional over the entire FACT operating voltage range of 2.0 to 5.5 VDC. These
devices have buffered outputs that will drive CMOS or TTL devices with no additional interface
circuitry. HD74ACT devices have the same output structures as HD74AC devices.
1
FACT Descriptions and Family Characteristics
1.3 Low Power CMOS Operation
If there is one single characteristic that justifies the existence of CMOS, it is low power dissipation. In the
quiescent state, FACT draws three orders of magnitude less power than the equivalent LS or ALS TTL
device. This enhances system reliability; because costly regulated high current power supplies, heat sinks
and fans are eliminated. FACT logic devices are ideal for portable systems such as laptop computers and
backpack communications systems. Operating power is also very low for FACT logic. Power
consumption of various technologies with a clock frequency of 1 MHz is shown below.
•
FACT = 0.1 mW/gate
•
ALS = 1.2 mW/gate
•
LS = 2.0 mW/gate
•
HC = 0.1 mW/gate
Figure 1 illustrates the effects of I
CC
versus power supply voltage (V
CC
) for two load capacitance values: 50
pF and stray capacitance. The clock frequency was 1 MHz for the measurements.
500
400
I
CC
(µA)
300
200
100
0
0
2
4
V
CC
(Volts)
6
C
L
= Fixture Capacitance
@ 1 MHz
C
L
= 50 pF @ 1 MHz
Figure 1 I
CC
vs V
CC
1.4 AC Performance
In comparison to LS, ALS and HC families, FACT devices have faster internal gate delays as well as the
basic gate delays. Additionally, as the level of integration increases, FACT logic leads the way to very
high-speed systems.
The example below describes typical values for a HD74XX138, 3 to 8 line decoder.
•
•
•
•
FACT = 6.0 ns @ C
L
= 50 pF
ALS = 12.0 ns @ C
L
= 50 pF
LS = 27.0 ns @ C
L
= 15 pF
HC = 17.0 ns @ C
L
= 50 pF
2
FACT Descriptions and Family Characteristics
AC performance specifications are guaranteed at 5.0 V
±
0.5 V and 3.3 V
±
0.3 V. For worst case design at
2.0 V V
CC
on all device types, the formula below can be used to determine AC performance.
AC performance at 2.0 V V
CC
= 1.9
×
AC specification at 3.3 V
1.5 Multiple Output Switching
Propagation delay is affected by the number of outputs switching simultaneously. Typically, devices with
more than one output will follow the rule: for each output switching, derate the databook specification by
250 ps. This effect typically is not significant on an octal device unless more than four outputs are
switching simultaneously. This derating is valid for the entire temperature range and 5.0 V
±
10% V
CC
.
1.6 Noise Immunity
The noise immunity of a logic family is also an important equipment cost factor in terms of decoupling
components, power supply dynamic resistance and regulation as well as layout rules for PC boards and
signal cables.
The comparisons shown describe the difference between the input threshold of a device and the output
voltage, |V
IL
–V
OL
| / |V
IH
–V
OH
| at 4.5 V V
CC
.
•
FACT = 1.25/1.25 V
•
ALS = 0.4/0.7 V
•
LS = 0.3/0.7 V@ 4.75 V V
CC
•
HC = 1.25/1.25 V
1.7 Output Characteristics
All FACT outputs are buffered to ensure consistent output voltage and current specifications across the
family. Both HD74AC and HD74ACT device types have the same output structures. Two clamp diodes
are internally connected to the output pin to suppress voltage overshoot and undershoot in noisy system
applications witch can result from impedance mismatching. The balanced output design allows for
controlled edge rates and equal rise and fall times.
All devices (HD74AC or HD74ACT) are guaranteed to source and sink 24 mA. HD74AC/ACTXXX, are
capable of driving 50
Ω
transmission lines.
1.7.1 I
OL
/I
OH
Characteristics
•
•
•
•
FACT = 24/–24 mA
ALS = 24/–15 mA
LS = 8/–0.4 mA @ 4.75 V V
CC
HC = 4/–4 mA
3
FACT Descriptions and Family Characteristics
1.7.2 Dynamic Output Drive
Traditionally, in order to predict what incident wave voltages would occur in a system, the designer was
required to do an output analysis using a Bergeron diagram. Not only is this a long and time-consuming
operation, but the designer needed to depend upon the accuracy and reliability of the manufacturer-supplied
‘typical’ output I/V curve. Additionally, there was no way to guarantee that any supplied device would
meet these ‘typical’ performance values across the operating voltage and temperature limits. Hitachi has
taken the necessary steps to guarantee incident wave switching on transmission lines with impedances as
low as 50
Ω.
Figure 2 shows a Bergerton diagram for switching both high-to-low and low-to-high. On the right side of
the graph (I
out
> 0), are the V
OH
and I
IH
curves for FACT logic while on the left side (I
out
< 0), are the curves
for V
OL
and I
IL
. Although we will only discuss here the low-to-high transition, the information presented
may be applied to a high-to-low transition.
7
6
5
Volts (V)
4
3
2
1
0
–1
–2
–0.2
–0.1
0
Current (A)
0.1
0.2
V
OL
/I
OL
HIGH-to-LOW
Slope = 50
Ω
V
IN
/I
IN
Line 2
Slope = 50
Ω
V
OH
/I
OH
Line 1
LOW-to-HIGH
Figure 2 Gate Driving 50
Ω
Line Reflection Diagram
Begin analysis at the V
OL
(quiescent) point. This is the intersection of the V
OL
/I
OL
curve for the output and
the V
IN
/I
IN
curve for the input. For CMOS inputs and outputs, this point will be approximately 100 mV.
Then draw a 50
Ω
load line from this intersection to the V
OH
/I
OH
curve as shown by Line 1. This
intersection is the voltage that the incident wave will have. Here it occurs at approximately 3.95 V. Then
draw a line with a slope of –50
Ω
from this first intersection point to the V
IN
/I
IN
curve as shown by Line 2.
This second intersection will be the first reflection back from the input gate. Continue this process of
drawing the load line from each intersection to the next. Lines terminating on the V
OH
/I
OH
curve should
have positive slopes while lines terminating on the V
IN
/I
IN
curve should have negative slopes.
Each intersection point predicts the voltage of each reflected wave on the transmission line. Intersection
points on the V
OH
/I
OH
curve will be waves travelling from the driver to the receiver while intersection points
on the V
IN
/I
IN
curve will be waves travelling from the receiver to the driver.
Figure 3 and 4 show the resultant waveforms. Each division on the time scale represents the propagation
delay of the transmission line.
4
