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Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
Cautions
Keep safety first in your circuit designs!
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Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
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contained therein.
HD74HC259
8-bit Addressable Latch
ADE-205-480 (Z)
1st. Edition
Sep. 2000
Description
The HD74HC259 has a single data input (D), 8 latch outputs (Q
0
-Q
7
), 3 address inputs (A, B, and C), a
common enable input (E), and a common clear input. To operate this device as an addressable latch, data is
held on the D input, and the address of the latch into which the data is to be entered is held on the A, B and
C inputs. When enable is taken low the data flows through to the addressed output. The data is stored
when enable transitions from low to high. All unaddressed latches will remain unaffected. With enable in
the high state the device is deselected, and all latches remain in their previous state, unaffected by changes
on the data or address inputs. To eliminate the possibility of entering erroneous data into the latches, the
enable should be held high (inactive) while the address lines are changing.
If enable is held high and clear is taken low all eight latches are cleared to a low state. If enable is low all
latches except the addressed latch will be cleared. The addressed latch will instead follow the D input,
effectively implementing a 3-to-8 line decoder.
Features
•
•
•
•
•
High Speed Operation: t
pd
(Data to Output) = 16 ns typ (C
L
= 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: V
CC
= 2 to 6 V
Low Input Current: 1
µA
max
Low Quiescent Supply Current: I
CC
(static) = 4
µA
max (Ta = 25°C)
Function Table
Inputs
Clear
H
H
L
L
G
L
H
L
H
Output of Addressed Latch
D
Qio
D
L
Each Other Output
Qio
Qio
L
L
Function
Addressable latch
Memory
8-line demultiplexer
Clear
HD74HC259
Select Inputs
C
L
L
L
L
H
H
H
H
B
L
L
H
H
L
L
H
H
A
L
H
L
H
L
H
L
H
Latch Addressed
0
1
2
3
4
5
6
7
Notes: 1. D: the level at the data input
2. Qio: the level of Qi (i = 0, 1, ···7, as apropriate) before the indicated steady-state input conditions
were established.
Pin Arrangement
A
Latch
select
B
C
Q
0
Q
1
Outputs
Q
2
Q
3
GND
1
2
3
4
5
6
7
8
B
C
Q
0
Q
1
Q
2
Q
3
Q
4
A
CLR
G
D
Q
7
Q
6
Q
5
16 V
CC
15 Clear
14 Enable
13
Data
input
12 Q
7
11 Q
6
Outputs
10 Q
5
9 Q
4
(Top view)
2
HD74HC259
DC Characteristics
Ta = 25°C
Item
Input voltage
Symbol
V
IH
Ta = –40 to
+85°C
Max
—
—
—
0.5
1.35
1.8
—
—
—
—
—
0.1
0.1
0.1
0.33
0.33
±1.0
40
µA
µA
I
OL
= 4 mA
I
OL
= 5.2 mA
Vin = V
CC
or GND
Vin = V
CC
or GND, Iout = 0
µA
V
I
OH
= –4 mA
I
OH
= –5.2 mA
Vin = V
IH
or V
IL
I
OL
= 20
µA
V
Vin = V
IH
or V
IL
I
OH
= –20
µA
V
Unit
V
Test Conditions
V
CC
(V) Min Typ Max Min
2.0
4.5
6.0
1.5 —
3.15 —
4.2 —
—
—
—
—
—
—
—
—
—
0.5
1.5
3.15
4.2
—
V
IL
2.0
4.5
6.0
1.35 —
1.8
—
1.9
4.4
5.9
4.13
5.63
—
—
—
Output voltage
V
OH
2.0
4.5
6.0
4.5
6.0
1.9 2.0 —
4.4 4.5 —
5.9 6.0 —
4.18 —
5.68 —
—
—
—
—
—
—
—
—
—
V
OL
2.0
4.5
6.0
4.5
6.0
0.0 0.1
0.0 0.1
0.0 0.1
—
—
—
—
0.26 —
0.26 —
±0.1
—
4.0
—
Input current
Quiescent supply
current
Iin
I
CC
6.0
6.0
3
