HD74HC390
Dual Decade Counters
REJ03D0624-0200
(Previous ADE-205-503)
Rev.2.00
Mar 30, 2006
Description
The HD74HC390 incorporate dual decade counters, each composed of a divide-by-two and a divide-by-five counter.
The divide-by-two and divide-by-five counters can be cascaded to form dual decade, dual bi-quinary, or various
combinations up to a single divide-by-100 counter.
The HD74HC390 is incremented on the high to low transition (negative edge) of the clock input, and each has an
independent clear input. When clear is set high all four bits of each counter are set to a low level. This enables count
truncation and allows the implementation of divide-by-N counter configurations.
Features
•
High Speed Operation: t
pd
(Clock A to Q
A
) = 11 ns typ (C
L
= 50 pF)
•
High Output Current: Fanout of 10 LSTTL Loads
•
Wide Operating Voltage: V
CC
= 2 to 6 V
•
Low Input Current: 1
µA
max
•
Low Quiescent Supply Current: I
CC
(static) = 4
µA
max (Ta = 25°C)
•
Ordering Information
Part Name
HD74HC390P
HD74HC390FPEL
Package Type
DILP-16 pin
SOP-16 pin (JEITA)
Package Code
(Previous Code)
PRDP0016AE-B
(DP-16FV)
P
Package
Abbreviation
—
EL (2,000 pcs/reel)
Taping Abbreviation
(Quantity)
PRSP0016DH-B
FP
(FP-16DAV)
Note: Please consult the sales office for the above package availability.
Function Table
Clock
A
X
B
X
X
Clear
H
L
L
Operation
Clear
÷2
and
÷5
Increment
÷2
Increment
÷5
Note:
X
1. H; High level, L; Low level, X; Irrelevant, Z; High impedance
Rev.2.00 Mar 30, 2006 page 1 of 6
HD74HC390
Pin Arrangement
1A
1Clear
1Q
A
Output
1B
1Q
B
Outputs
1
2
3
4
5
6
7
8
(Top view)
CLR
1Q
A
1A
1B
1Q
B
CLR
2Q
A
2A
2B
2Q
B
2Q
C
16 V
CC
15 2A
14 2Clear
13
2Q
A
Output
12 2B
11 2Q
B
10 2Q
C
9
2Q
D
Outputs
1Q
C
1Q
D
GND
1Q
C
1Q
D
2Q
D
Logic Diagram
Clear
A
CK
D
Q
CK
R
Q
A
B
CK
D
Q
CK
R
Q
B
CK
D
Q
CK
R
Q
C
CK
D
Q
CK
R
Q
D
Rev.2.00 Mar 30, 2006 page 2 of 6
HD74HC390
Absolute Maximum Ratings
Item
Supply voltage range
Input / Output voltage
Input / Output diode current
Output current
V
CC
, GND current
Power dissipation
Symbol
V
CC
V
IN
, V
OUT
I
IK
, I
OK
I
OUT
I
CC
or I
GND
P
T
Ratings
–0.5 to 7.0
–0.5 to V
CC
+0.5
±20
±25
±50
500
Unit
V
V
mA
mA
mA
mW
Storage temperature
Tstg
–65 to +150
°C
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
Recommended Operating Conditions
Item
Supply voltage
Input / Output voltage
Operating temperature
Input rise / fall time
Note:
*1
Symbol
V
CC
V
IN
, V
OUT
Ta
t
r
, t
f
Ratings
2 to 6
0 to V
CC
–40 to 85
0 to 1000
0 to 500
Unit
V
V
°C
ns
Conditions
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
0 to 400
1. This item guarantees maximum limit when one input switches.
Waveform: Refer to test circuit of switching characteristics.
Electrical Characteristics
Item
Input voltage
Symbol V
CC
(V)
V
IH
2.0
4.5
6.0
2.0
4.5
6.0
Output voltage
V
OH
2.0
4.5
6.0
4.5
V
OL
6.0
2.0
4.5
6.0
4.5
6.0
Input current
Quiescent supply
current
Iin
I
CC
6.0
6.0
Ta = 25°C
Min
Typ Max
1.5
3.15
4.2
—
—
—
1.9
4.4
5.9
4.18
5.68
—
—
—
—
—
—
—
—
—
—
—
—
—
2.0
4.5
6.0
—
—
0.0
0.0
0.0
—
—
—
—
—
—
—
0.5
1.35
1.8
—
—
—
—
—
0.1
0.1
0.1
0.26
0.26
±0.1
4.0
Ta = –40 to+85°C
Unit
Min
Max
1.5
3.15
4.2
—
—
—
1.9
4.4
5.9
4.13
5.63
—
—
—
—
—
—
—
—
—
—
0.5
1.35
1.8
—
—
—
—
—
0.1
0.1
0.1
0.33
0.33
±1.0
40
I
OH
= 4 mA
I
OH
= 5.2 mA
µA
Vin = V
CC
or GND
µA
Vin = V
CC
or GND, Iout = 0
µA
V
Vin = V
IH
or V
IL
V
Vin = V
IH
or V
IL
I
OH
= –20
µA
V
Test Conditions
V
IL
V
I
OH
= –4 mA
I
OH
= –5.2 mA
I
OL
= 20
µA
Rev.2.00 Mar 30, 2006 page 3 of 6
HD74HC390
Switching Characteristics
(C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Ta = 25°C
Item
Maximum clock
frequency
Propagation delay
time
Symbol V
CC
(V)
f
max
2.0
4.5
6.0
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Pulse width
t
w
2.0
4.5
6.0
2.0
4.5
6.0
Output rise/fall
time
Input capacitance
t
TLH
t
THL
Cin
2.0
4.5
6.0
—
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
80
16
14
25
5
4
—
—
—
—
Typ
—
—
—
—
11
—
—
32
—
—
16
—
—
20
—
—
15
—
—
14
—
—
8
—
—
1
—
—
5
—
5
Max
5
27
32
120
24
20
290
58
49
130
26
22
185
37
31
130
26
22
165
33
28
—
—
—
—
—
—
75
15
13
10
Ta = –40 to +85°C
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
100
20
17
31
6
5
—
—
—
—
Max
4
21
25
150
30
26
365
73
62
165
33
28
230
46
39
165
33
28
205
41
35
—
—
—
—
—
—
95
19
16
10
ns
ns
ns
Clock B to Q
D
ns
ns
Clock A to Q
A
Unit
MHz
Test Conditions
ns
Clock A to Q
C
(Q
A
connected to Clock B)
Clock B to Q
B
ns
Clock B to Q
C
ns
Clear to Q
A
, Q
B
, Q
C
, Q
D
Removal time
t
h
ns
pF
Test Circuit
V
CC
V
CC
Output
Q
A
Q
B
Q
C
Clear
Q
D
C
L
= 50 pF
See Function Table
Input
Pulse Generator
Z
out
= 50
Ω
Input
Pulse Generator
Z
out
= 50
Ω
A
B
Output
Output
Output
C
L
= 50 pF
C
L
= 50 pF
C
L
= 50 pF
Note : 1. C
L
includes probe and jig capacitance.
Rev.2.00 Mar 30, 2006 page 4 of 6
HD74HC390
Waveforms
•
Waveform – 1
t
r
t
f
V
CC
Clock
50%
50%
50%
50%
t
w
t
w
t
PHL (Measure at tn+2)
90%
50%
10%
0V
t
PLH (Measure at tn+1)
90%
50%
10%
V
OH
V
OL
V
OH
V
OL
Q
A
t
THL
t
PHL (Measure at tn+4)
90%
50%
10%
t
TLH
t
PLH (Measure at tn+2)
90%
50%
10%
Q
B
t
THL
t
PHL (Measure at tn+8)
90%
t
TLH
t
PLH (Measure at tn+4)
90%
50%
10%
V
OH
V
OL
Q
C
50%
10%
t
THL
t
TLH
t
PHL (Measure at tn+10)
t
PLH (Measure at tn+8)
90%
90%
50%
10%
50%
10%
V
OH
V
OL
Q
D
t
THL
t
TLH
Notes: 1. Input waveform: PRR
≤
1 MHz, Zo = 50
Ω,
t
r
≤
6 ns, t
f
≤
6 ns
2. tn is bit time with all outputs at low.
•
Waveform – 2
t
r
90 %
50 % 50 %
10 %
t
w(clear)
t
PHL
90%
t
f
V
CC
10 %
0V
Clear
V
OH
50 %
10%
Q
A
to Q
D
V
OL
t
THL
Notes: 1. Input waveform: PRR
≤
1 MHz, Zo = 50
Ω,
t
r
≤
6 ns, t
f
≤
6 ns
2. The output are measured one at a time with one transition per measurement.
Rev.2.00 Mar 30, 2006 page 5 of 6
