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HD74SSTV16857AN

SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48, TVSOP-48

器件类别:逻辑    逻辑   

厂商名称:Renesas(瑞萨电子)

厂商官网:https://www.renesas.com/

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器件参数
参数名称
属性值
厂商名称
Renesas(瑞萨电子)
零件包装代码
SOIC
包装说明
TSSOP,
针数
48
Reach Compliance Code
compliant
系列
SSTV
JESD-30 代码
R-PDSO-G48
长度
9.7 mm
逻辑集成电路类型
D FLIP-FLOP
位数
14
功能数量
1
端子数量
48
最高工作温度
70 °C
最低工作温度
输出极性
TRUE
封装主体材料
PLASTIC/EPOXY
封装代码
TSSOP
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟(tpd)
2.8 ns
认证状态
Not Qualified
座面最大高度
1.2 mm
最大供电电压 (Vsup)
2.7 V
最小供电电压 (Vsup)
2.3 V
标称供电电压 (Vsup)
2.5 V
表面贴装
YES
温度等级
COMMERCIAL
端子形式
GULL WING
端子节距
0.4 mm
端子位置
DUAL
触发器类型
POSITIVE EDGE
宽度
4.4 mm
最小 fmax
200 MHz
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To all our customers
Regarding the change of names mentioned in the document, such as Hitachi
Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand
names are mentioned in the document, these names have in fact all been changed to Renesas
Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and
corporate statement, no changes whatsoever have been made to the contents of the document, and
these changes do not constitute any alteration to the contents of the document itself.
Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
Cautions
Keep safety first in your circuit designs!
1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better
and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corporation product best suited to the customer's application; they do not convey any
license under any intellectual property rights, or any other rights, belonging to Renesas Technology
Corporation or a third party.
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third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.
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algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corporation without notice due to product improvements or
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or system that is used under circumstances in which human life is potentially at stake. Please contact
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8. Please contact Renesas Technology Corporation for further details on these materials or the products
contained therein.
HD74SSTV16857A
1:1 14-bit SSTL_2 Registered Buffer
ADE-205-695 (Z)
Rev.0
Jun. 2002
Description
The HD74SSTV16857A is a 14-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and
LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input.
Data flow from D to Q is controlled by differential clock pins (CLK,
CLK)
and the
RESET.
Data is
triggered on the positive edge of the positive clock (CLK), and the negative clock (CLK) must be used to
maintain noise margins. When
RESET
is low, all registers are reset and all outputs are low.
To ensure defined outputs from the register before a stable clock has been supplied,
RESET
must be held
in the low state during power up.
Features
Supports LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input
Differential SSTL_2 (Stub series terminated logic) CLK signal
Flow through architecture optimizes PCB layout
Package type
Package type
TSSOP-48 pin
TVSOP-48 pin
Package code
TTP-48DBV
TTP-48DEV
Package suffix
T
N
Taping code
EL (1,000 pcs / Reel)
EL (1,000 pcs / Reel)
HD74SSTV16857A
Function Table
Inputs
RESET
L
H
H
H
H:
L:
X:
:
↓:
Note:
CLK
X
L or H
CLK
X
H or L
D
X
H
L
X
L
H
L
Q
0
*1
Output Q
High level
Low level
Immaterial
Low to high transition
High to low transition
1. Output level before the indicated steady state input conditions were established.
Rev.0, Jun. 2002, page 2 of 2
HD74SSTV16857A
Pin Arrangement
Q1 1
Q2 2
GND 3
V
DDQ
4
Q3 5
Q4 6
Q5 7
GND 8
V
DDQ
9
Q6 10
Q7 11
V
DDQ
12
GND 13
Q8 14
Q9 15
V
DDQ
16
GND 17
Q10 18
Q11 19
Q12 20
V
DDQ
21
GND 22
Q13 23
Q14 24
48 D1
47 D2
46 GND
45 V
CC
44 D3
43 D4
42 D5
41 D6
40 D7
39
CLK
38 CLK
37 V
CC
36 GND
35 V
REF
34
RESET
33 D8
32 D9
31 D10
30 D11
29 D12
28 V
CC
27 GND
26 D13
25 D14
(Top view)
Rev.0, Jun. 2002, page 3 of 3
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