RED
YELLOW
HIGH EFFICIENCY RED
GREEN
HIGH EFFICIENCY GREEN
SOFT ORANGE
0.200" 8-Character 5x7 Dot Matrix Parallel Input
Alphanumeric Intelligent Display
®
Devices
Dimensions in inches (mm)
1.680 (42.67) max.
0.210
(5.34)
0.105
(2.67)
0.771
(19.58)
0.386
(9.8)
Pin 1 Indicator
Part Number
EIA Date
Code
HDSP211X
SIEMENS WW
0.189
(4.79)
0.018 typ.
(.46)
Z
1
0.160±.020
(4.06±.50)
0.012 (0.30) typ.
Intensity Code
Color Bin
(For Yellow Only)
0.209 (5.31)
0.086
(2.19)
HDSP2110S
HDSP2111S
HDSP2112S
HDSP2113S
HDSP2114S
HDSP2115S
0.189
(4.81)
0.600
(15.24)
FEATURES
• Eight 0.200" Dot Matrix Characters in Red, Yellow,
High Efficiency Red, Green, High Efficiency Green,
or Soft Orange
• Built-in 128 Character ROM,
Mask Programmable for Custom Fonts
• Readable from 8 Feet (2.5 meters)
• Built-in Decoders, Multiplexers and Drivers
• Wide Viewing Angle, X Axis
±
55
°
, Y Axis
±
65
°
• Programmable Features:
– Individual Flashing Character
– Full Display Blinking
– Multi-Level Dimming and Blanking
– Clear Function
– Self Test
• Internal or External Clock
• End Stackable Dual-In-Line Plastic Package
• Read/Write Capability
• 16 User Definable Characters
0.100
(2.54) typ.
DESCRIPTION
The HDSP2110S (Red), HDSP2111S (Yellow), HDSP2112S (High Effi-
ciency Red), HDSP2113S (Green), HDSP2114S (High Efficiency
Green), and HDSP2115S (Soft Orange) are eight digit, 5x7 dot matrix,
alphanumeric Intelligent Display devices. The 0.20 inch high digits are
packaged in a rugged, high quality, optically transparent, 0.6 inch lead
spacing, 28 pin plastic DIP.
The on-board CMOS has a built-in 128 character ROM. The
HDSP211XS also has a user definable character (UDC) feature, which
uses a RAM that permits storage of 16 arbitrary characters, symbols
or icons that are software-definable by the user. The character ROM
itself is mask programmable and easily modified by the manufacturer
to provide specified custom characters.
The HDSP211XS is designed for standard microprocessor interface
techniques, and is fully TTL compatible. The Clock I/O and Clock
Select pins allow the user to cascade multiple display modules.
1
ESD Warning:
Standard precautions for CMOS
handling should be observed.
Switching specifications
(over operating temperature range and V
CC
=4.5 V)
Symbol
Tacc
Tacc
Tacs
Tce
Tce
Tach
Tcer
Tces
Tces
Tceh
Tw
Twd
Description
Display Access Time—Write
Display Access Time—Read
Address Setup Time to CE
Chip Enable Active Time—Write
Chip Enable Active Time—Read
Address Hold Time to CE
Chip Enable Recovery Time
Chip Enable Active Prior to
Rising Edge—Write
Chip Enable Active Prior to
Rising Edge—Read
Chip Enable Hold to Rising Edge
of Read/Write Signal
Write Active Time
Data Valid Prior to
Rising Edge of Write Signal
Data Write Time
Chip Enable Active Prior to Valid
Data
Read Active Prior to Valid Data
Read Data Float Delay
Reset Active Time
Min.
210
230
10
140
160
20
60
140
160
0
100
50
20
160
95
10
300
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µ
s
ns
ns
Maximum Ratings
(T
A
=25
°
C)
DC Supply Voltage, V
CC
to GND
(max. voltage with no LEDs on)................... –0.3 to +7.0 VDC
Input Voltage Levels,
All Inputs........................................................–0.3 to V
CC
+0.3
Operating Temperature ........................................–40
°
C to 85
°
C
Storage Temperature..........................................–40
°
C to 100
°
C
Relative Humidity (non-condensing).................................... 85%
Operating Voltage, V
CC
to GND
(Max. voltage with 20 dots/digits on)...............................5.5 V
Maximum Solder Temperature
(0.063" below seating plane, t<5 sec)............................260
°
C
ESD Protection at 1.5 K
Ω
,
100 pF........................................................V
Z
=4 KV (each pin)
Figure 1. Enlarged character font
Dimensions in inches (mm)
0.112
(2.85)
C1 C2 C3 C4 C5
0.030 (0.76) Typ.
R1
R2
R3
0.01 (0.254)
R4
R5
R6
R7
0.189
(4.81)
Tdh
Tr
Trd
Tdf
Trc
0.026 (0.65) Typ.
Figure 2. Write cycle timing diagram
Tacc
A0-A3
FL
Tach
Tacs
CE
Tces
Tw
WR
Twd
D0-D7
Input pulse levels –0.6 V to 2.4 V
Tacs
Tcer
Tce
Tceh
Tdh
HDSP2110S/1S/2S/3S/4S/5S
2
Figure 3. Read cycle timing diagram
Tacc
A0-A3
FL
Tacs
CE
Tces
Tr
RD
Trd
D0-D7
Tdf
Tceh
Tach
Tce
Tcer
Tacs
Cascading Displays
The HDSP211XS oscillator is designed to drive up to 16 other
HDSP211XSs with input loading of 15 pF each.
The following are the general requirements for cascading 16
displays together:
• Determine the correct address for each display.
• Use CE from an address decoder to select the correct
display.
• Select one of the Displays to provide the clock for the other
displays. Connect CLKSEL to V
CC
for this display.
• Tie CLKSEL to ground on other displays.
• Use RTS to synchronize the blinking between the displays.
Figure 4. Cascading diagram
RD
WR
FL
RST
V
CC
RD WR
FL
RST CLK I/O CLKSEL
Display
D0-D7 A0-A4
Data I/O
Address
RD WR
Up to14 More Displays
in between
FL
RST CLK I/O CLKSEL
Display
CE
D0-D7 A0-A4
CE
A6
A7
A8
A9
0
Address
Decoder Address Decode Chip 1 to 14
15
HDSP2110S/1S/2S/3S/4S/5S
3
Optical characteristics at 25
°
C
(V
CC
=5.0 V at full brightness)
Red HDSP2110S
Description
Peak Luminous Intensity
(1)
Peak Wavelength
Dominant Wavelength
Yellow HDSP2111S
Description
Peak Luminous Intensity
(1)
Peak Wavelength
Dominant Wavelength
High Efficiency Red HDSP2112S
Description
Peak Luminous Intensity
(1)
Peak Wavelength
Dominant Wavelength
Green HDSP2113S
Description
Peak Luminous Intensity
(1)
Peak Wavelength
Dominant Wavelength
High Efficiency Green HDSP2114S
Description
Peak Luminous Intensity
(1)
Peak Wavelength
Dominant Wavelength
Soft Orange HDSP2115S
Description
Peak Luminous Intensity
(1)
Peak Wavelength
Dominant Wavelength
Note:
1)
Symbol
I
V
peak
λ
(peak)
λ
(d)
Min.
70
Typ.
90
660
639
Units
µ
cd/dot
nm
nm
Symbol
I
V
peak
λ
(peak)
λ
(d)
Min.
130
Typ.
210
583
585
Units
µ
cd/dot
nm
nm
Symbol
I
V
peak
λ
(peak)
λ
(d)
Min.
150
Typ.
330
630
620
Units
µ
cd/dot
nm
nm
Symbol
I
V
peak
λ
(peak)
λ
(d)
Min.
150
Typ.
260
565
570
Units
µ
cd/dot
nm
nm
Symbol
I
V
peak
λ
(peak)
λ
(d)
Min.
200
Typ.
510
568
574
Units
µ
cd/dot
nm
nm
Symbol
I
V
peak
λ
(peak)
λ
(d)
Min.
150
Typ.
270
610
604
Units
µ
cd/dot
nm
nm
Peak luminous intensity is measured at T
A
=T
J
=25
°
C. No time is allowed for the device to warm up prior to measurement.
HDSP2110S/1S/2S/3S/4S/5S
4
Electrical characteristics at 25
°
C
Parameters
Limits
Min.
V
CC
I
CC
Blank
I
CC
12 dots/digit on
(1) (2)
I
CC
20 dots/digit on
(1) (2)
I
ILP
(with pull-up)
Input Leakage
I
IL
(no pull-up)
Input Leakage
V
IH
Input Voltage High
V
IL
Input Voltage Low
V
OL
(D0–D7), Output Voltage Low
V
OL
(CLK), Output Voltage Low
V
OH
Output Voltage High
θ
JC
Thermal Resistance,
Junction to Case
Clock I/O Frequency
FM, Digit Multiplex Frequency
Blinking Rate
Clock I/O Buss Loading
Clock Out Rise Time
Clock Out Fall Time
Notes:
1)
2)
Conditions
Typ.
5.0
0.65
185
284
Max.
5.5
1.0
255
370
–5
Units
V
mA
mA
mA
µA
µA
V
V
0.4
0.4
V
V
V
25
°C/W
81.14
362.5
2.83
2.40
500
500
KHz
Hz
Hz
pF
nsec
nsec
V
CC
=4.5 V, V
OH
=2.4 V
V
CC
=4.5 V, V
OH
=0.4 V
V
CC
=4.5 to 5.5 V
V
CC
=4.5 to 5.5 V
V
CC
=5 V, V
IN
=5 V
V
CC
=5 V, “V” in all 8 digits
V
CC
=5 V, “#” in all 8 digits
V
CC
=5 V, V
IN
=0 V to V
CC
,
(WR, CE, FL, RST, RD, CLKSEL)
V
CC
=5 V, V
IN
=0–5 V,
(CLK, A0–A3, D0–D7)
V
CC
=4.5 V to 5.5 V
V
CC
=4.5 V to 5.5 V
V
CC
=4.5 V, I
OL
=1.6 mA
V
CC
=4.5 V, I
OL
=40
µA
V
CC
=4.5 V, I
OH
=–40
µA
4.5
–18
–11
–1
2.0
GND
–0.3
+1
V
CC
+0.3
2.4
28
125
0.98
57.34
256
2.0
I
CC
is an average value.
I
CC
is measured with the display at full brightness. Peak I
CC
=
28
/
15
I
CC
average (#displayed).
Recommended operating conditions
(T
A
=–40
°
C to +85
°
C)
Parameter
Supply Voltage
Input Voltage Low
Input Voltage High
Output Voltage Low
Output Voltage High
Symbol
V
CC
V
IL
V
IH
V
OL
V
OH
2.4
2.0
0.4
Min.
4.5
Max.
5.5
0.8
Units
V
V
V
V
V
HDSP2110S/1S/2S/3S/4S/5S
5
