High Efficiency Delay Lines
HE2LA(A,B)T***D Series
1.0 Description
These High-Efficiency delay lines are used for clock and data deskew in differential circuit designs requiring pre-
cise timing control in a small, low profile BGA package. The differential delay lines are constructed as broad-
side-coupled transmission lines on ceramic. These designs feature characteristics similar to unshielded twisted-
pair cable.
2.0 Mechanical
-
Please refer to page 43 for land pattern
Size A
1
a
b
c
d
2
3
Side B
1.1 Max
1
a
2
3
4
1.1 Max
1.27 3.81
±0.20
Ball Dia = 28 mil (0.711 mm)
6.35 ±0.20
b1
c1
b3
c3
0.075
6.35
±0.20
b
10.16
±0.20
Ball Dia = 28 mil (0.711 mm)
0.075
dimension mm
a3
a2
b3
b2
3.0 Electrical
Size Designator:
Delay Range:
Standard Delay Increment:
Delay Tolerance (provisional):
Differential Impedance:
DC Resistance:
Rated Current:
Temp. Coeff. of Time Delay
Insulation Resistance:
Isolation Resistance:
Operating Temperature:
Storage Temperature:
A
B
0.1 to 0.6 ns
0.1 to 1.6 ns
0.1 ns
0.1 ns
± (15 ps + 2% of nominal)
100 ohms ± 10%
< 2 ohm/ns
100 mA
< 150 ppm/C
> 100 Mohms @100 VDC
> 100 Mohms @ 100 VDC
-40°C to +85°C
-55°C to +125°C
4.0 Part Number
HE
2
L
A
*
T
***
D
T
Product family
Number of signal lines
Product type
Impedance (A = 100 ohms)
Size designator
Termination type
Delay ‘ns’ x 100 (0.5 ns = 050)
Application type
Tape& reel designator
5
Tape & reel quantity (5 = 500 pcs per reel)
R
R
EG
I
S
TERE
EG
I
S
TERE
D
ISO9001 ISO14001
A4
303
Manufacturer(s) of the products described on this page are indicated by their respective logos.
D
A8
561
6