HEF4017B
5-stage Johnson decade counter
Rev. 04 — 9 December 2008
Product data sheet
1. General description
The HEF4017B is a 5-stage Johnson decade counter with ten spike-free decoded active
HIGH outputs (Q0 to Q9), an active LOW carry output from the most significant flip-flop
(Q5-9), active HIGH and active LOW clock inputs (CP0, CP1) and an overriding
asynchronous master reset input (MR).
The counter is advanced by either a LOW-to-HIGH transition at CP0 while CP1 is LOW or
a HIGH-to-LOW transition at CP1 while CP0 is HIGH (see
Table 3).
When cascading counters, the Q5-9 output, which is LOW while the counter is in states 5,
6, 7, 8, and 9, can be used to drive the CP0 input of the next counter. A HIGH on MR
resets the counter to zero (Q0 = Q5-9 = HIGH; Q1 to Q9 = LOW) independent of the clock
inputs (CP0, CP1).
Automatic counter code correction is provided by an internal circuit: following any illegal
code the counter returns to a proper counting mode within 11 clock pulses.
Schmitt trigger action makes the clock inputs highly tolerant of slower rise and fall times.
It operates over a recommended V
DD
power supply range of 3 V to 15 V referenced to V
SS
(usually ground). Unused inputs must be connected to V
DD
, V
SS
, or another input. It is
also suitable for use over both the industrial (−40
°C
to +85
°C)
and automotive (−40
°C
to
+125
°C)
temperature ranges.
2. Features
I
I
I
I
I
I
I
I
Automatic counter correction
Tolerant of slow clock rise and fall times
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Operates across the automotive temperature range
−40 °C
to +125
°C
Complies with JEDEC standard JESD 13-B
ESD protection:
N
HBM JESD22-A114E exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
3. Applications
I
Industrial and automotive
NXP Semiconductors
HEF4017B
5-stage Johnson decade counter
4. Ordering information
Table 1.
Ordering information
All types operate from
−
40
°
C to +125
°
C
Type number
HEF4017BP
HEF4017BT
Package
Name
DIP16
SO16
Description
plastic dual in-line package; 16-leads (300 mil)
plastic small outline package; 16 leads; body width 3.9 mm
Version
SOT38-4
SOT109-1
5. Functional diagram
13
14
15
CP1
CP0
MR
5-STAGE JOHNSON COUNTER
DECODING AND OUTPUT CIRCUITRY
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
3
2
4
7
10
1
5
6
9
11
Q5-9
12
001aah242
Fig 1.
Functional diagram
D
CP1
CP0
Q
FF
1
CP Q
RD
D
Q
FF
2
CP Q
RD
Q
FF
3
CP Q
RD
D
D
Q
FF
4
CP Q
RD
D
Q
FF
5
CP Q
RD
MR
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q5-9
001aah243
Fig 2.
Logic diagram
HEF4017B_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 9 December 2008
2 of 16
NXP Semiconductors
HEF4017B
5-stage Johnson decade counter
14
13
14
CP1
CP0
Q0
Q1
Q2
Q3
Q4
Q5
Q6
15
MR
Q7
Q8
Q9
Q5-9
001aah239
CTRDIV10/DEC
&
CT = 0
0
1
2
3
4
5
6
7
8
9
CT≥5
001aah240
3
2
4
7
10
1
5
6
9
11
12
3
2
4
7
10
1
5
6
9
11
12
13
15
Fig 3.
Logic symbol
Fig 4.
IEE logic symbol
6. Pinning information
6.1 Pinning
HEF4017B
Q5
Q1
Q0
Q2
Q6
Q7
Q3
V
SS
1
2
3
4
5
6
7
8
001aae574
16 V
DD
15 MR
14 CP0
13 CP1
12 Q5-9
11 Q9
10 Q4
9
Q8
Fig 5.
Pin configuration
6.2 Pin description
Table 2.
Symbol
Q0 to Q9
V
SS
Q5-9
CP1
Pin description
Pin
3, 2, 4, 7, 10, 1, 5, 6, 9, 11
8
12
13
Description
decoded output
ground supply voltage
carry output (active LOW)
clock input (HIGH-to-LOW edge-triggered)
HEF4017B_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 9 December 2008
3 of 16
NXP Semiconductors
HEF4017B
5-stage Johnson decade counter
Table 2.
Symbol
CP0
MR
V
DD
Pin description
…continued
Pin
14
15
16
Description
clock input (LOW-to-HIGH edge-triggered)
master reset input
supply voltage
7. Functional description
Table 3.
MR
H
L
L
L
L
L
L
[1]
Function table
[1]
CP0
X
H
↑
L
X
H
↓
CP1
X
↓
L
X
H
↑
L
Operation
Q0 = Q5-9 = H; Q1 to Q9 = L
counter advances
counter advances
no change
no change
no change
no change
H = HIGH voltage level; L = LOW voltage level; X = don’t care;
↑
= positive-going transition;
↓
= negative-going transition.
HEF4017B_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 9 December 2008
4 of 16
NXP Semiconductors
HEF4017B
5-stage Johnson decade counter
CP0 INPUT
CP1 INPUT
MR INPUT
Q0 OUTPUT
Q1 OUTPUT
Q2 OUTPUT
Q3 OUTPUT
Q4 OUTPUT
Q5 OUTPUT
Q6 OUTPUT
Q7 OUTPUT
Q8 OUTPUT
Q9 OUTPUT
Q5-9 OUTPUT
001aah244
Fig 6.
Timing diagram
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DD
I
IK
V
I
I
OK
I
I/O
Parameter
supply voltage
input clamping current
input voltage
output clamping current
input/output current
V
O
< 0.5 V or V
O
> V
DD
+ 0.5 V
V
I
< 0.5 V or V
I
> V
DD
+ 0.5 V
Conditions
Min
−0.5
-
−0.5
-
-
Max
+18
±10
V
DD
+ 0.5
±10
±10
Unit
V
mA
V
mA
mA
HEF4017B_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 9 December 2008
5 of 16
