INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF40374B
MSI
Octal D-type flip-flop with 3-state
outputs
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
Octal D-type flip-flop with 3-state outputs
DESCRIPTION
The HEF40374B is an octal D-type flip-flop with 3-state
buffered outputs with a common clock input (CP). The
device is used primarily as an 8-bit positive edge-triggered
storage register for interfacing with a 3-state bus. Data on
the D-inputs is transferred to storage during the
LOW-to-HIGH transition of the clock (CP) input. The
3-state output buffers are controlled by an active LOW
output enable input (EO). A HIGH on EO forces the eight
outputs to a high impedance OFF-state. When EO is
LOW, the data in the register appears at the outputs.
HEF40374B
MSI
The output stages have high current output capability
suitable for driving highly capacitive loads.
The device features hysteresis on the CP input to improve
noise rejection.
Schmitt-trigger action in the E input makes the circuit
highly tolerant to slower input rise and fall times.
The HEF40374B is pin and functionally compatible with
the TTL ‘374’ device.
Supply voltage range: 3 to 15 V.
Fig.1 Functional diagram.
Fig.2 Pinning diagram.
PINNING
HEF40374BP(N): 20-lead DIL; plastic (SOT146-1)
HEF40374BD(F):
HEF40374BT(D):
20-lead DIL; ceramic (cerdip)
(SOT152)
20-lead SO; plastic (SOT163-1)
D
0
to D
7
CP
EO
O
0
to O
7
data inputs
clock input
output enable input (active LOW)
3-state buffered outputs
( ): Package Designator North America
FAMILY DATA, I
DD
LIMITS category MSI
See Family Specifications
January 1995
2
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January 1995
3
Fig.3 Logic diagram.
Philips Semiconductors
Octal D-type flip-flop with 3-state outputs
HEF40374B
MSI
Product specification
Philips Semiconductors
Product specification
Octal D-type flip-flop with 3-state outputs
FUNCTION TABLE
INPUTS
OPERATING MODES
EO
L
load & read register
L
H
load register & disable outputs
Notes
1. H = HIGH state (the more positive voltage)
h = HIGH state (one set-up time prior to the LOW-to-HIGH clock transition)
L = LOW state (the less positive voltage)
I = LOW state (one set-up time prior to the LOW-to-HIGH clock transition)
Z = high impedance OFF-state
= LOW-to-HIGH clock transition
H
CP
D
n
I
h
I
h
INTERNAL
REGISTER
L
H
L
H
HEF40374B
MSI
OUTPUTS
O
0
TO O
7
L
H
Z
Z
January 1995
4
Philips Semiconductors
Product specification
Octal D-type flip-flop with 3-state outputs
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
See Family Specifications, except for:
D.C. current into any input
D.C. source or sink current into any output
D.C. current into the supply terminals
DC CHARACTERISTICS
V
SS
= 0 V
V
DD
V
V
OH
V
V
OL
V
SYMBOL
T
amb
(°C)
−40
MIN.
Output current
HIGH
Output current
HIGH
Output current
LOW
Hysteresis
voltage at
clock input (CP)
5
10
15
5
10
15
5
10
15
5
10
15
V
H
4,6
9,5
13,5
3,6
8,4
13,2
0,4
0,5
1,5
I
OL
−I
OH
−I
OH
0,75
1,85
14,5
9,3
14,4
19,5
2,9
9,5
30,0
TYP.
+
25
MIN.
0,6
1,5
15
10
15
20
2,3
7,6
25
TYP.
1,2
3,0
50
24
46
62
5,4
17
45
220
250
320
±
I
I
±
I
O
±
I
max.
max.
max.
HEF40374B
MSI
10 mA
25 mA
100 mA
+
85
MIN.
0,45
1,1
15,5
10,7
15,0
19,8
1,75
5,50
19,0
TYP.
mA
mA
mA
mA
mA
mA
mA
mA
mA
mV
mV
mV
(1) P-channel MOS transistor conducting.
(2) P-channel MOS transistor and bipolar
n-p-n transistor conducting.
Fig.4 Typical output source current characteristic.
Fig.5 Schematic diagram of output stage.
January 1995
5
