INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4040B
MSI
12-stage binary counter
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
12-stage binary counter
DESCRIPTION
The HEF4040B is a 12-stage binary ripple counter with a
clock input (CP), an overriding asynchronous master reset
input (MR) and twelve fully buffered outputs (O
0
to O
11
).
The counter advances on the HIGH to LOW transition of
CP. A HIGH on MR clears all counter stages and forces all
outputs LOW, independent of CP. Each counter stage is a
static toggle flip-flop. Schmitt-trigger action in the clock
input makes the circuit highly tolerant to slower clock rise
and fall times.
HEF4040B
MSI
Fig.1 Functional diagram.
PINNING
CP
MR
O
0
to O
11
clock input (HIGH to LOW edge-triggered)
master reset input (active HIGH)
parallel outputs
APPLICATION INFORMATION
Some examples of applications for the HEF4040B are:
•
Frequency dividing circuits
•
Time delay circuits
Fig.2 Pinning diagram.
•
Control counters
FAMILY DATA, I
DD
LIMITS category MSI
HEF4040BP(N):
HEF4040BD(F):
HEF4040BT(D):
16-lead DIL; plastic
(SOT38-1)
16-lead DIL; ceramic (cerdip)
(SOT74)
16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
12-stage binary counter
HEF4040B
MSI
Fig.3 Logic diagram.
AC CHARACTERISTICS
V
SS
= 0 V; T
amb
= 25
°C;
C
L
= 50 pF; input transition times
≤
20 ns
V
DD
V
Propagation delays
CP
→
O
0
HIGH to LOW
5
10
15
5
LOW to HIGH
O
n
→
O
n
+
1
HIGH to LOW
10
15
5
10
15
5
LOW to HIGH
MR
→
O
n
HIGH to LOW
Output transition times
HIGH to LOW
10
15
5
10
15
5
10
15
5
LOW to HIGH
10
15
January 1995
3
t
TLH
t
THL
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
105
45
35
85
40
30
35
15
10
35
15
10
90
40
30
60
30
20
60
30
20
210
90
70
170
80
60
70
30
20
70
30
20
180
80
60
120
60
40
120
60
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
78 ns
34 ns
27 ns
58 ns
29 ns
22 ns
note 1
note 1
note 1
note 1
note 1
note 1
63 ns
29 ns
22 ns
10 ns
9 ns
6 ns
10 ns
9 ns
6 ns
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
(0,55 ns/pF) C
L
(0,23 ns/pF) C
L
(0,16 ns/pF) C
L
(0,55 ns/pF) C
L
(0,23 ns/pF) C
L
(0,16 ns/pF) C
L
(0,55 ns/pF) C
L
(0,23 ns/pF) C
L
(0,16 ns/pF) C
L
(0,55 ns/pF) C
L
(0,23 ns/pF) C
L
(0,16 ns/pF) C
L
(0,55 ns/pF) C
L
(0,23 ns/pF) C
L
(0,16 ns/pF) C
L
(1,0 ns/pF) C
L
(0,42 ns/pF) C
L
(0,28 ns/pF) C
L
(1,0 ns/pF) C
L
(0,42 ns/pF) C
L
(0,28 ns/pF) C
L
SYMBOL
MIN. TYP. MAX.
TYPICAL EXTRAPOLATION
FORMULA
Philips Semiconductors
Product specification
12-stage binary counter
HEF4040B
MSI
SYMBOL
MIN. TYP. MAX.
50
t
WCPH
30
20
40
t
WMRH
30
20
40
t
RMR
30
20
10
f
max
15
25
25
15
10
20
15
10
20
15
10
20
30
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
see also waveforms
Fig.4
TYPICAL EXTRAPOLATION
FORMULA
V
DD
V
Minimum clock
pulse width; HIGH
Minimum MR
pulse width; HIGH
Recovery time
for MR
Maximum clock
pulse frequency
5
10
15
5
10
15
5
10
15
5
10
15
Note
1. For other loads than 50 pF at the n
th
output, use the slope given.
V
DD
V
Dynamic power
dissipation per
package (P)
5
10
15
TYPICAL FORMULA FOR P (µW)
400 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
2 000 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
5 200 f
i
+ ∑
(f
o
C
L
)
×
V
DD2
where
f
i
= input freq. (MHz)
f
o
= output freq. (MHz)
C
L
= load cap. (pF)
∑
(f
o
C
L
) = sum of outputs
V
DD
= supply voltage (V)
January 1995
4
Philips Semiconductors
Product specification
12-stage binary counter
HEF4040B
MSI
Fig.4
Waveforms showing propagation delays for MR to O
n
and CP to O
0
, minimum MR and CP pulse widths.
January 1995
5
