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HEF4043BT653

Linear Voltage Regulators Ultralow Noise 150mA CMOS

器件类别:半导体    逻辑   

厂商名称:NXP(恩智浦)

厂商官网:https://www.nxp.com

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器件参数
参数名称
属性值
产品种类
Product Category
Latches
制造商
Manufacturer
NXP(恩智浦)
RoHS
Details
Number of Circuits
4 Circuit
Logic Type
CMOS
Logic Family
HEF4000
Polarity
Non-Inverting
Quiescent Current
80 uA
Number of Output Lines
4 Line
High Level Output Current
- 3.6 mA
Low Level Output Current
32 mA
传播延迟时间
Propagation Delay Time
25 ns at 15 V
电源电压-最大
Supply Voltage - Max
15.5 V
电源电压-最小
Supply Voltage - Min
4.5 V
最小工作温度
Minimum Operating Temperature
- 40 C
最大工作温度
Maximum Operating Temperature
+ 85 C
封装 / 箱体
Package / Case
SO-16
系列
Packaging
Reel
系列
Packaging
MouseReel
系列
Packaging
Cut Tape
Function
Transparent
高度
Height
1.45 mm
长度
Length
10 mm
安装风格
Mounting Style
SMD/SMT
Number of Channels
4 Channels
Number of Input Lines
8 Line
工作电源电压
Operating Supply Voltage
3.3 V, 5 V, 9 V, 12 V
输出类型
Output Type
3-State
Reset Type
No Reset
工厂包装数量
Factory Pack Quantity
2500
类型
Type
S-R Type
宽度
Width
4 mm
单位重量
Unit Weight
0.007079 oz
文档预览
HEF4043B
Quad R/S latch with 3-state outputs
Rev. 11 — 24 March 2016
Product data sheet
1. General description
The HEF4043B is a quad R/S latch with 3-state outputs with a common output enable
input (OE). Each latch has an active HIGH set input (1S to 4S), an active HIGH reset input
(1R to 4R) and an active HIGH 3-state output (1Q to 4Q).
When OE is HIGH, the latch output (nQ) is determined by the nR and nS inputs as shown
in
Table 3.
When OE is LOW, the latch outputs are in the high impedance OFF-state. OE
does not affect the state of the latch. The high impedance off-state feature allows common
bussing of the outputs.
It operates over a recommended V
DD
power supply range of 3 V to 15 V referenced to V
SS
(usually ground). Unused inputs must be connected to V
DD
, V
SS
, or another input.
2. Features and benefits
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from
40 C
to +85
C
Complies with JEDEC standard JESD 13-B
3. Applications
Four-bit storage with output enable
4. Ordering information
Table 1.
Ordering information
All types operate from
40
C to +85
C.
Type number
HEF4043BT
Package
Name
SO16
Description
plastic small outline package; 16 leads; body width 3.9 mm
Version
SOT109-1
Nexperia
HEF4043B
Quad R/S latch with 3-state outputs
5. Functional diagram
Fig 1.
Functional diagram
Fig 2.
Logic diagram for one latch
6. Pinning information
6.1 Pinning
Fig 3.
Pin configuration
HEF4043B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 11 — 24 March 2016
2 of 13
Nexperia
HEF4043B
Quad R/S latch with 3-state outputs
6.2 Pin description
Table 2.
Symbol
1Q to 4Q
1R to 4R
1S to 4S
OE
V
SS
n.c.
V
DD
Pin description
Pin
2, 9, 10, 1
3, 7, 11, 15
4, 6, 12, 14
5
8
13
16
Description
3-state buffered latch output
reset input (active HIGH)
set input (active HIGH)
common output enable input
ground supply voltage
not connected
supply voltage
7. Functional description
Table 3.
Inputs
OE
L
H
H
H
[1]
Function table
[1]
Output
nS
X
L
H
L
nR
X
H
X
L
nQ
Z
L
H
latched
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high impedance state.
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DD
I
IK
V
I
I
OK
I
I/O
I
DD
T
stg
T
amb
P
tot
P
[1]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
input/output current
supply current
storage temperature
ambient temperature
total power dissipation
power dissipation
Conditions
V
I
<
0.5
V or V
I
> V
DD
+ 0.5 V
V
O
<
0.5
V or V
O
> V
DD
+ 0.5 V
Min
0.5
-
0.5
-
-
-
65
40
Max
+18
10
V
DD
+ 0.5
10
10
50
+150
+85
500
100
Unit
V
mA
V
mA
mA
mA
C
C
mW
mW
T
amb
40 C
to +85
C
SO16 package
per output
[1]
-
-
For SO16 package: P
tot
derates linearly with 8 mW/K above 70
C.
HEF4043B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 11 — 24 March 2016
3 of 13
Nexperia
HEF4043B
Quad R/S latch with 3-state outputs
9. Recommended operating conditions
Table 5.
Symbol
V
DD
V
I
T
amb
t/V
Recommended operating conditions
Parameter
supply voltage
input voltage
ambient temperature
input transition rise and fall rate
in free air
V
DD
= 5 V
V
DD
= 10 V
V
DD
= 15 V
Conditions
Min
3
0
40
-
-
-
Typ
-
-
-
-
-
-
Max
15
V
DD
+85
3.75
0.5
0.08
Unit
V
V
C
s/V
s/V
s/V
10. Static characteristics
Table 6.
Static characteristics
V
SS
= 0 V; V
I
= V
SS
or V
DD
unless otherwise specified.
Symbol Parameter
V
IH
HIGH-level input voltage
Conditions
I
O
< 1
A
V
DD
5V
10 V
15 V
V
IL
LOW-level input voltage
I
O
< 1
A
5V
10 V
15 V
V
OH
HIGH-level output voltage
I
O
< 1
A
5V
10 V
15 V
V
OL
LOW-level output voltage
I
O
< 1
A
5V
10 V
15 V
I
OH
HIGH-level output current
V
O
= 2.5 V
V
O
= 4.6 V
V
O
= 9.5 V
V
O
= 13.5 V
I
OL
LOW-level output current
V
O
= 0.4 V
V
O
= 0.5 V
V
O
= 1.5 V
I
I
I
OZ
input leakage current
OFF-state output current
nQ output HIGH;
returned to V
DD
nQ output LOW;
returned to V
SS
5V
5V
10 V
15 V
5V
10 V
15 V
15 V
15 V
15 V
T
amb
=
40 C
T
amb
= 25
C
Min
3.5
7.0
11.0
-
-
-
4.95
9.95
14.95
-
-
-
-
-
-
-
0.52
1.3
3.6
-
-
-
Max
-
-
-
1.5
3.0
4.0
-
-
-
0.05
0.05
0.05
1.7
0.52
1.3
3.6
-
-
-
0.3
1.6
1.6
Min
3.5
7.0
11.0
-
-
-
4.95
9.95
14.95
-
-
-
-
-
-
-
0.44
1.1
3.0
-
-
-
Max
-
-
-
1.5
3.0
4.0
-
-
-
0.05
0.05
0.05
1.4
0.44
1.1
3.0
-
-
-
0.3
1.6
1.6
T
amb
= 85
C
Unit
Min
3.5
7.0
11.0
-
-
-
4.95
9.95
14.95
-
-
-
-
-
-
-
0.36
0.9
2.4
-
-
-
Max
-
-
-
1.5
3.0
4.0
-
-
-
0.05
0.05
0.05
1.1
0.9
2.4
-
-
-
1.0
12.0
12.0
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
A
A
A
0.36
mA
HEF4043B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 11 — 24 March 2016
4 of 13
Nexperia
HEF4043B
Quad R/S latch with 3-state outputs
Table 6.
Static characteristics
…continued
V
SS
= 0 V; V
I
= V
SS
or V
DD
unless otherwise specified.
Symbol Parameter
I
DD
supply current
Conditions
I
O
= 0 A
V
DD
5V
10 V
15 V
C
I
input capacitance
T
amb
=
40 C
T
amb
= 25
C
Min
-
-
-
-
Max
20
40
80
-
Min
-
-
-
-
Max
20
40
80
7.5
T
amb
= 85
C
Unit
Min
-
-
-
-
Max
150
300
600
-
A
A
A
pF
11. Dynamic characteristics
Table 7.
Dynamic characteristics
V
SS
= 0 V; T
amb
= 25
C; For waveforms and test circuit see
Section 12;
unless otherwise specified.
Symbol
t
PHL
Parameter
HIGH to LOW
propagation delay
Conditions
nR nQ;
see
Figure 4
V
DD
5V
10 V
15 V
t
PLH
LOW to HIGH
propagation delay
nS nQ;
see
Figure 4
5V
10 V
15 V
t
t
transition time
nQ output;
see
Figure 4
5V
10 V
15 V
t
PHZ
HIGH to OFF-state
propagation delay
OE nQ;
see
Figure 5
5V
10 V
15 V
t
PLZ
LOW to OFF-state
propagation delay
OE nQ;
see
Figure 5
5V
10 V
15 V
t
PZH
OFF-state to HIGH
propagation delay
OE nQ;
see
Figure 5
5V
10 V
15 V
t
PZL
OFF-state to LOW
propagation delay
OE nQ;
see
Figure 5
5V
10 V
15 V
t
W
pulse width
nS input HIGH; 5 V
minimum width; 10 V
see
Figure 4
15 V
nR input HIGH; 5 V
minimum width; 10 V
see
Figure 4
15 V
[1]
[2]
[1] [2]
[1]
[1]
Extrapolation formula
63 ns + (0.55 ns/pF)C
L
24 ns + (0.23 ns/pF)C
L
17 ns + (0.16 ns/pF)C
L
38 ns + (0.55 ns/pF)C
L
14 ns + (0.23 ns/pF)C
L
7 ns + (0.16 ns/pF)C
L
10 ns + (1.00 ns/pF)C
L
9 ns + (0.42 ns/pF)C
L
6 ns + (0.28 ns/pF)C
L
Min
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
30
20
16
30
20
16
Typ
90
35
25
65
25
15
60
30
20
45
20
10
50
20
10
25
15
10
40
20
15
15
10
8
15
10
8
Max
180
70
50
135
50
35
120
60
40
90
35
25
100
40
25
50
30
25
80
45
35
-
-
-
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (C
L
in pF).
t
t
is the same as t
THL
and t
TLH
.
All information provided in this document is subject to legal disclaimers.
©
HEF4043B
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 11 — 24 March 2016
5 of 13
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参数对比
与HEF4043BT653相近的元器件有:HEF4043BT652、HEF4043BP652。描述及对比如下:
型号 HEF4043BT653 HEF4043BT652 HEF4043BP652
描述 Linear Voltage Regulators Ultralow Noise 150mA CMOS Switching Voltage Regulators Latches QUAD R/S LATCH
产品种类
Product Category
Latches Latches Latches
制造商
Manufacturer
NXP(恩智浦) NXP(恩智浦) NXP(恩智浦)
RoHS Details Details Details
Number of Circuits 4 Circuit 4 Circuit 4 Circuit
Logic Type CMOS CMOS CMOS
Logic Family HEF4000 HEF4000 HEF4000
Polarity Non-Inverting Non-Inverting Non-Inverting
Quiescent Current 80 uA 80 uA 80 uA
Number of Output Lines 4 Line 4 Line 4 Line
High Level Output Current - 3.6 mA - 3.6 mA - 3.6 mA
Low Level Output Current 32 mA 32 mA 32 mA
传播延迟时间
Propagation Delay Time
25 ns at 15 V 25 ns at 15 V 25 ns at 15 V
电源电压-最大
Supply Voltage - Max
15.5 V 15.5 V 15.5 V
电源电压-最小
Supply Voltage - Min
4.5 V 4.5 V 4.5 V
最小工作温度
Minimum Operating Temperature
- 40 C - 40 C - 40 C
最大工作温度
Maximum Operating Temperature
+ 85 C + 85 C + 85 C
封装 / 箱体
Package / Case
SO-16 SO-16 PDIP-16
Function Transparent Transparent Transparent
高度
Height
1.45 mm 1.45 mm 3.2 mm
长度
Length
10 mm 10 mm 19.5 mm
安装风格
Mounting Style
SMD/SMT SMD/SMT Through Hole
Number of Channels 4 Channels 4 Channels 4 Channels
Number of Input Lines 8 Line 8 Line 8 Line
工作电源电压
Operating Supply Voltage
3.3 V, 5 V, 9 V, 12 V 3.3 V, 5 V, 9 V, 12 V 3.3 V, 5 V, 9 V, 12 V
输出类型
Output Type
3-State 3-State 3-State
Reset Type No Reset No Reset No Reset
工厂包装数量
Factory Pack Quantity
2500 1000 1000
类型
Type
S-R Type S-R Type S-R Type
宽度
Width
4 mm 4 mm 6.48 mm
单位重量
Unit Weight
0.007079 oz 0.007079 oz 0.057419 oz
系列
Packaging
Cut Tape Tube Tube
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