HEF4049B
Hex inverting buffers
Rev. 11 — 23 June 2016
Product data sheet
1. General description
The HEF4049B provides six inverting buffers with high current output capability suitable
for driving TTL or high capacitive loads. Since input voltages in excess of the buffers’
supply voltage are permitted, the buffers may also be used to convert logic levels of up to
15 V to standard TTL levels. Their guaranteed fan-out into common bipolar logic elements
is shown in
Table 3.
It operates over a recommended V
DD
power supply range of 3 V to 15 V referenced to V
SS
(usually ground). Unused inputs must be connected to V
DD
, V
SS
, or another input.
2. Features and benefits
Accepts input voltages in excess of the supply voltage
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from
40 C
to +85
C
Complies with JEDEC standard JESD 13-B
3. Applications
LOCMOS (Local Oxidation CMOS) to DTL/TTL converter
HIGH sink current for driving two TTL loads
HIGH-to-LOW level logic conversion
4. Ordering information
Table 1.
Ordering information
All types operate from
40
C to +85
C.
Type number
HEF4049BT
Package
Name
SO16
Description
plastic small outline package; 16 leads; body width 3.9 mm
Version
SOT109-1
Nexperia
HEF4049B
Hex inverting buffers
5. Functional diagram
Fig 1.
Logic symbol
Fig 2.
Logic diagram for one gate
Fig 3.
Input protection circuit
HEF4049B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 11 — 23 June 2016
2 of 12
Nexperia
HEF4049B
Hex inverting buffers
6. Pinning information
6.1 Pinning
Fig 4.
Pin configuration
6.2 Pin description
Table 2.
Symbol
V
DD
1Y to 6Y
1A to 6A
V
SS
n.c.
Pin description
Pin
1
2, 4, 6, 10, 12, 15
3, 5, 7, 9, 11, 14
8
13, 16
Description
supply voltage
output
input
ground supply voltage
not connected
7. Functional description
Table 3.
Guaranteed fan-out
Guaranteed fan-out
2
9
16
Driven element
Standard TTL
74 LS
74 L
HEF4049B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 11 — 23 June 2016
3 of 12
Nexperia
HEF4049B
Hex inverting buffers
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DD
I
IK
V
I
I
OK
I
I/O
I
DD
T
stg
T
amb
P
tot
P
[1]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
input/output current
supply current
storage temperature
ambient temperature
total power dissipation
power dissipation
Conditions
V
I
<
0.5
V
V
O
<
0.5
V or V
O
> V
DD
+ 0.5 V
Min
0.5
10
0.5
-
-
-
65
40
Max
+18
-
+18
10
10
50
+150
+85
500
100
Unit
V
mA
V
mA
mA
mA
C
C
mW
mW
T
amb
40 C
to +85
C
SO16 package
per output
[1]
-
-
For SO16 package: P
tot
derates linearly with 8 mW/K above 70
C.
9. Recommended operating conditions
Table 5.
Symbol
V
DD
V
I
T
amb
t/V
Recommended operating conditions
Parameter
supply voltage
input voltage
ambient temperature
input transition rise and fall rate
in free air
V
DD
= 5 V
V
DD
= 10 V
V
DD
= 15 V
Conditions
Min
3
0
40
-
-
-
Typ
-
-
-
-
-
-
Max
15
15
+85
3.75
0.5
0.08
Unit
V
V
C
s/V
s/V
s/V
10. Static characteristics
Table 6.
Static characteristics
V
SS
= 0 V; V
I
= V
SS
or V
DD
unless otherwise specified.
Symbol Parameter
V
IH
HIGH-level input voltage
Conditions
I
O
< 1
A
V
DD
5V
10 V
15 V
V
IL
LOW-level input voltage
I
O
< 1
A
5V
10 V
15 V
T
amb
=
40 C
Min
3.5
7.0
11.0
-
-
-
Max
-
-
-
1.5
3.0
4.0
T
amb
= 25
C
Min
3.5
7.0
11.0
-
-
-
Max
-
-
-
1.5
3.0
4.0
T
amb
= 85
C
Min
3.5
7.0
11.0
-
-
-
Max
-
-
-
1.5
3.0
4.0
V
V
V
V
V
V
Unit
HEF4049B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 11 — 23 June 2016
4 of 12
Nexperia
HEF4049B
Hex inverting buffers
Table 6.
Static characteristics
…continued
V
SS
= 0 V; V
I
= V
SS
or V
DD
unless otherwise specified.
Symbol Parameter
V
OH
HIGH-level output voltage
Conditions
I
O
< 1
A
V
DD
5V
10 V
15 V
V
OL
LOW-level output voltage
I
O
< 1
A
5V
10 V
15 V
I
OH
HIGH-level output current
V
O
= 2.5 V
V
O
= 4.6 V
V
O
= 9.5 V
V
O
= 13.5 V
I
OL
LOW-level output current
V
O
= 0.4 V
V
O
= 0.5 V
V
O
= 1.5 V
I
I
I
DD
input leakage current
supply current
V
DD
= 15 V
I
O
= 0 A
5V
5V
10 V
15 V
4.75 V
10 V
15 V
15 V
5V
10 V
15 V
C
I
input capacitance
T
amb
=
40 C
Min
4.95
9.95
14.95
-
-
-
-
-
-
-
3.5
12.0
24.0
-
-
-
-
-
Max
-
-
-
0.05
0.05
0.05
1.7
0.52
1.3
3.6
-
-
-
0.3
4.0
8.0
16.0
-
T
amb
= 25
C
Min
4.95
9.95
14.95
-
-
-
-
-
-
-
2.9
10.0
20.0
-
-
-
-
-
Max
-
-
-
0.05
0.05
0.05
1.4
0.44
1.1
3.0
-
-
-
0.3
4.0
8.0
16.0
7.5
T
amb
= 85
C
Min
4.95
9.95
14.95
-
-
-
-
-
-
-
2.3
8.0
16.0
-
-
-
-
-
Max
-
-
-
0.05
0.05
0.05
1.1
0.9
2.4
-
-
-
1.0
30
60
120
-
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
A
A
A
A
pF
Unit
0.36
mA
11. Dynamic characteristics
Table 7.
Dynamic characteristics
V
SS
= 0 V; C
L
= 50 pF; t
r
= t
f
20 ns; T
amb
= 25
C; unless otherwise specified.
Symbol
t
PHL
Parameter
HIGH to LOW
propagation delay
Conditions
nA to nY;
see
Figure 5
V
DD
5V
10 V
15 V
t
PLH
LOW to HIGH
propagation delay
nA to nY;
see
Figure 5
5V
10 V
15 V
t
THL
HIGH to LOW output
transition time
see
Figure 5
5V
10 V
15 V
t
TLH
LOW to HIGH output
transition time
see
Figure 5
5V
10 V
15 V
[1]
[1]
[1]
[1]
[1]
Extrapolation formula
26 ns + (0.18 ns/pF)C
L
11 ns + (0.08 ns/pF)C
L
9 ns + (0.05 ns/pF)C
L
23 ns + (0.55 ns/pF)C
L
14 ns + (0.23 ns/pF)C
L
12 ns + (0.16 ns/pF)C
L
3 ns + (0.35 ns/pF)C
L
3 ns + (0.14 ns/pF)C
L
2 ns + (0.09 ns/pF)C
L
10 ns + (1.00 ns/pF)C
L
9 ns + (0.42 ns/pF)C
L
6 ns + (0.28 ns/pF)C
L
Min
-
-
-
-
-
-
-
-
-
-
-
-
Typ
35
15
12
50
25
20
20
10
7
60
30
20
Max
70
30
25
100
50
40
40
20
14
120
60
40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (C
L
in pF).
HEF4049B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 11 — 23 June 2016
5 of 12
