HEF4526B
Programmable 4-bit binary down counter
Rev. 5 — 22 November 2011
Product data sheet
1. General description
The HEF4526B is a synchronous programmable 4-bit binary down counter with active
HIGH and active LOW clock inputs (CP0, CP1), an asynchronous parallel load input (PL),
four parallel inputs (A0 to A3), a cascade feedback input (CF), four buffered parallel
outputs (Q0 to Q3), a terminal count output (TC), an overriding asynchronous master
reset input (MR) and a decoded TC output that can be used for divide-by-n applications.
In single stage applications the TC output is connected to PL. CF allows cascade
divide-by-n operation with no additional gates required.
Information on A0 to A3 is loaded into the counter while PL is HIGH, independent of all
other inputs except MR, which must be LOW. When PL and CP1 are LOW, the counter
advances on a LOW-to-HIGH transition of CP0. When PL is LOW and CP0 is HIGH, the
counter advances on a HIGH to LOW transition of CP1. TC is HIGH when the counter is in
the zero state (Q0 = Q1 = Q2 = Q3 = LOW) and CF is HIGH and PL is LOW. A HIGH on
MR resets the counter (Q0 to Q3 = LOW) independent of other inputs. The clock input is
highly tolerant of slower clock rise and fall times due to Schmitt trigger action.
It operates over a recommended V
DD
power supply range of 3 V to 15 V referenced to V
SS
(usually ground). Unused inputs must be connected to V
DD
, V
SS
, or another input.
2. Features and benefits
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from
40 C
to +85
C
Complies with JEDEC standard JESD 13-B
3. Ordering information
Table 1.
Ordering information
All types operate from
40
C to +85
C.
Type number
HEF4526BP
HEF4526BT
Package
Name
DIP16
SO16
Description
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads; body width 3.9 mm
Version
SOT38-4
SOT109-1
NXP Semiconductors
HEF4526B
Programmable 4-bit binary down counter
4. Functional diagram
3
PL
5
A0
11
A1
14
A2
2
A3
PARALLEL LOAD
CIRCUITRY
6 CP0
CD/SD
CP
CD
Q3 1
Q2 15
BINARY
DOWN
COUNTER
4 CP1
10 MR
Q1 9
Q0 7
13 CF
ZERO
DETECTOR
TC 12
001aae719
Fig 1.
Functional diagram
1
CP0 input
CP1 input
MR input
Q0
Q1
Q2
Q3
2
4
8
16
32
64
128
256
512 1024 2048 4096
001aak014
Fig 2.
Timing diagram
HEF4526B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 22 November 2011
2 of 19
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Product data sheet
Rev. 5 — 22 November 2011
3 of 19
HEF4526B
NXP Semiconductors
A0
Q0
A1
Q1
A2
Q2
A3
Q3
PL
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
MR
CD1 CD2
O
FF
T
1
O
SD
CD1 CD2
O
FF
T
2
O
SD
CD1 CD2
O
FF
T
3
O
SD
CD1 CD2
O
FF
T
4
O
SD
CP1
Programmable 4-bit binary down counter
CP0
CF
TC
HEF4526B
001aae722
Fig 3.
Logic diagram
NXP Semiconductors
HEF4526B
Programmable 4-bit binary down counter
5. Pinning information
5.1 Pinning
HEF4526B
Q3
A3
PL
CP1
A0
CP0
Q0
V
SS
1
2
3
4
5
6
7
8
001aae720
16 V
DD
15 Q2
14 A2
13 CF
12 TC
11 A1
10 MR
9
Q1
Fig 4.
Pin configuration
5.2 Pin description
Table 2.
Symbol
A0 to A3
PL
CP0
CP1
CF
MR
TC
Q0 to Q3
V
DD
V
SS
Pin description
Pin
5, 11, 14, 2
3
6
4
13
10
12
7, 9, 15, 1
16
8
Description
parallel input
parallel load input
clock input (LOW-to-HIGH, triggered)
clock input (HIGH-to-LOW, triggered)
cascade feedback input
asynchronous master reset input
terminal count output
buffered parallel output
supply voltage
ground (0 V)
HEF4526B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 22 November 2011
4 of 19
NXP Semiconductors
HEF4526B
Programmable 4-bit binary down counter
6. Functional description
Table 3.
MR
H
L
L
L
L
L
L
L
[1]
Function table
[1]
PL
X
H
L
L
L
L
L
L
CP0
X
X
L
X
H
CP1
X
X
H
X
L
Mode
reset (asynchronous)
preset (asynchronous)
no change
no change
no change
no change
counter advances
counter advances
H = HIGH voltage level; L = LOW voltage level; X = don’t care;
= positive-going transition;
= negative-going transition.
Table 4.
Counting mode
CF = HIGH; PL = LOW; MR = LOW.
Count
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Outputs
Q3
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
Q2
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
Q1
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
Q0
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
HEF4526B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 22 November 2011
5 of 19
