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HI-1585

December 2015

MIL-STD-1553 / 1760

3.3V Dual Transceiver with Tail-Off Control

PIN CONFIGURATION

48 TOC2B

47 BUSBOUT

46 BUSBOUT

45 VDDB

44 BUSBOUT

43 BUSBOUT

42 BUSAOUT

41 BUSAOUT

40 VDDA

39 BUSAOUT

38 BUSAOUT

37 TOC2A

GND 1

VDDB 2

TXB 3

TXB 4

TXINHB 5

RXENB 6

RXB 7

RXB 8

GND 9

ENPEXTB 10

VDDB 11

BUSBIN 12

DESCRIPTION

The HI-1585 is an ultra-low power CMOS dual transceiver

designed to meet the requirements of the MIL-STD-1553

and MIL-STD-1760 specifications.

The transmitter section of each bus takes complementary

CMOS / TTL Manchester II bi-phase data and converts it to

differential voltages suitable for driving the bus isolation

transformer. Separate transmitter inhibit control signals are

provided for each transmitter.

The receiver section of the each bus converts the 1553 bus

bi-phase analog signals to complementary CMOS / TTL

data suitable for input to a Manchester decoder. Each bus

has its own Receive Enable input, which forces both

receive output signals to the bus idle state (logic "0") when

disabled.

To reduce end-of-transmission residual voltage offset

(”tail-off”), logic-level transmit signal inputs can be clocked-

in to synchronize their rise/fall transitions. This

compensates for timing mismatch or transmit signal path

propagation differences caused by board layout.

When sub-optimal board design consistently presents tail-

off magnitudes close to or exceeding mandatory limits,

another unique option lets the user select a bus-specific

level of digital tail-off compensation.

The HI-1585 also provides optional Receive output pulse

extension. With traditional MIL-STD-1553 transceivers,

low amplitude receive signals can result in RX/nRX pulses

less than 100ns wide. When this feature is enabled,

RX/nRX output pulse widths do not drop below 300ns,

greatly simplifying decoder design and enhancing noise

performance.

1585PCI

1585PCT

1585PCM

36 GND

35 VDDA

34 TXA

33 TXA

32 TXINHA

31 RXENA

30 RXA

29 RXA

28 GND

27 ENPEXTA

26 VDDA

25 BUSAIN

48 Pin Plastic 6mm x 6mm

Chip-Scale Package (QFN)

FEATURES

Compliant to MIL-STD-1553A and B,

MIL-STD-1760 and ARINC 708A

3.3V single supply operation

Smallest transceiver footprint available in

6mm x 6mm 48-pin plastic chip-scale

package (QFN)

Input data synchronization.

Tail-off compensation control.

Receiver output pulse-width extension

control.

APPLICATIONS

MIL-STD-1553 Terminals

Flight Control and Monitoring

Radar Systems

ECCM Interfaces

Stores Management

Test Equipment

Sensor Interfaces

Instrumentation

(DS1585 Rev. New)

HOLT INTEGRATED CIRCUITS

www.holtic.com

BUSBIN

VDDB

ENCLKB

CLKB

TOC1B

TOC0B

TOC0A

TOC1A

CLKA

ENCLKA

VDDA

BUSAIN

12/15

HI-1585

PIN DESCRIPTIONS

SYMBOL

GND

VDDB

TXB

TXINHB

RXENB

RXB

GND

ENPEXTB

VDDB

BUSBIN

VDDB

ENCLKB

CLKB

TOC1B

TOC0B

TOC0A

TOC1A

CLKA

ENCLKA

VDDA

BUSAIN

VDDA

ENPEXTA

GND

RXA

RXENA

TXINHA

TXA

VDDA

GND

TOC2A

BUSAOUT

VDDA

BUSAOUT

BUSBOUT

VDDB

BUSBOUT

TOC2B

FUNCTION

power supply

digital input

digital output

power supply

digital Input

power supply

analog input

power supply

digital input

power supply

analog input

power supply

digital Input

power supply

digital output

digital input

power supply

digital input

analog output

power supply

analog output

power supply

analog output

digital input

Ground

DESCRIPTION

+3.3 volt power for transceiver B

Transmitter B digital data input, non-inverted

Transmitter B digital data input, inverted

Receiver B enable. If low, forces RXB and RXB low

Receiver B output, non-inverted

Receiver B output, inverted

Ground

Enable pulse extension for receiver B

+3.3 volt power for transceiver B

MIL-STD-1553 bus input B, negative signal

MIL-STD-1553 bus input B, positive signal

+3.3 volt power for transceiver B

Enable input synchronization for transmitter B

Synchronization clock input for transmitter B

Tail-off adjust transmitter B. (See Table 2)

Tail-off adjust transmitter A. (See Table 2)

Synchronization clock input for transmitter A

Enable input synchronization for transmitter A

+3.3 volt power for transceiver A

MIL-STD-1553 bus input A, negative signal

MIL-STD-1553 bus input A, positive signal

+3.3 volt power for transceiver A

Enable pulse extension for receiver A

Ground

Receiver A output, inverted

Receiver A output, non-inverted

Receiver A enable. If low, forces RXA and RXA low

Transmitter A digital data input, non-inverted

Transmitter A digital data input, inverted

+3.3 volt power for transceiver A

Ground

Tail-off adjust transmitter A. (See Table 2)

MIL-STD-1553 bus driver A, positive signal

+3.3 volt power for transceiver A

MIL-STD-1553 bus driver A, negative signal

MIL-STD-1553 bus driver B, positive signal

+3.3 volt power for transceiver B

MIL-STD-1553 bus driver B, negative signal

Tail-off adjust transmitter B. (See Table 2)

Internal pull-down resistor

Internal pull-up resistor

Internal pull-down resistor

Transmit inhibit, bus A. If high BUSAOUT, BUSAOUT disabled Internal pull-down resistor

Internal pull-up resistor

Internal pull-down resistor

Internal pull-up resistor

Internal pull-down resistor

Internal pull-up resistor

Transmit inhibit, bus B. If high BUSBOUT, BUSBOUT disabled Internal pull-down resistor

Table 1. Pin Descriptions

HOLT INTEGRATED CIRCUITS

HI-1585

Each Bus (Bus A shown)

TRANSMITTER

TXINHA

TXA

BUSAOUT

CLKA

Data Bus

Isolation

Transformer

Slope

Control

BUSAOUT

Coupler

Network

Direct or

Transformer

TXA

ENCLKA

TOC2A

TOC1A

TOC0A

Offset

Adjust

RECEIVER

BUSAIN

RXA

Pulse

Extend

RXA

RXENA

ENPEXTA

Input

Filter

BUSAIN

Comparator

Figure 1. Block Diagram

HOLT INTEGRATED CIRCUITS

HI-1585

FUNCTIONAL DESCRIPTION

The HI-1585 dual MIL-STD-1553 bus transceiver contains

a differential voltage source driver and a differential analog

bus receiver for each bus. It is designed for applications us-

ing a MIL-STD-1553B communications bus. The device

generates a trapezoidal output waveform during transmis-

sion.

●

mismatched conductor length or impedance between en-

coder and transceiver drive signal inputs for TX and TX

mismatched positive/negative drive voltage in the

transceiver

mismatched positive/negative rise and fall times in the

transceiver

poor signal path impedance matching between trans-

ceiver positive/negative drive output pins and the iso-

lation transformer

imbalance between positive/negative half-windings in

the center-tapped isolation transformer.

TRANSMITTER

For each bus, data input to the HI-1585 transmitter is a pair

of complementary CMOS inputs TXA and TXA for Bus A,

with a corresponding signal pair for Bus B. The transmitter

accepts Manchester II bi-phase data and converts it to dif-

ferential analog voltages on BUSAOUT and BUSAOUT, or

BUSBOUT and BUSBOUT. The transceiver outputs are ei-

ther direct- or transformer-coupled to the MIL-STD-1553

data bus. Both coupling methods produce a nominal volt-

age on the bus of 7.5 Volts peak to peak.

The transmitter is automatically inhibited and placed in the

high impedance state when TXA and TXA (or TXB and

TXB) are both driven to the same logic state. A bus transmit-

ter is also forced to the high impedance state when logic “1”

is applied at the TXINHA (or TXINHB) transmit inhibit input,

regardless of the TXA and TXA (or TXB and TXB) input con-

dition.

TRANSMIT-INDUCED TAIL-OFF (OFFSET)

A prevalent concern when designing MIL-STD-1553 termi-

nals goes by a number of names, including transmit "output

symmetry", "tail-off" and "offset". This is a transmit-induced

phenomenon that occurs on the bus following long trans-

missions, when one or more design or operating factors are

less than ideal. Slight imbalances in the transmitted analog

signal voltage cause accumulation of energy in the termi-

nal's isolation transformer. When transmission ends and

the transceiver bus interface goes to the Standby or receive

mode, a temporary DC voltage is expressed on the bus.

This "tail-off" voltage can have positive or negative polarity;

it decays exponentially, often persisting for 10 to 20μs de-

pending on magnitude. See Figure 2. Good posi-

tive/negative signal matching (or short message transmis-

sions) result in low tail-off magnitude, while serious mis-

match problems combined with long transmissions can

cause the DC stub voltage to approach or exceed 0.25 V

peak-peak.

Design and product use factors that influence tail-off in-

clude:

●

Holt carefully designs its MIL-STD-1553 transceivers for sym-

metry and matched positive/negative drive characteristics to

minimize transceiver contribution to tail-off. We strongly urge

designers to prioritize system topology and layout so that MIL-

STD-1553 bus interface characteristics are considered first. All

too often, it seems like 1553 bus interface is a late consider-

ation, resulting in marginal performance (or worse) and consid-

erable time wasted on redesign.

Ideally, the isolation transformer is located close to the 1553

bus cable termination connector. The transceiver should be

close to the transformer with matched signal path conductors.

The Manchester II encoder (often implemented in FPGA or

CPLD) should be close to the transceiver and uses Hardware

Description Language (HDL) that carefully matches posi-

tive/negative time intervals and uses synchronous switching.

A design may deviate from ideal characteristics when circum-

stances prevail. Mismatch caused by layout deficiency often re-

sults in a consistent tail-off range for each bus, with message-

to-message tail-off magnitude changes caused by message

length and data differences. Bus A tail-off rarely matches Bus

B. Sometimes the contribution from various factors cancels

out, moving the tail-off voltage range for that bus closer to zero.

Sometimes the various contributions conspire to raise average

tail-off magnitude away from zero. Until now, designers had

few options other than redesign when unacceptable tail-off oc-

curred. The HI-1585 offers two optional provisions to minimize

systemic tail-off occurrence, namely Input Data Synchroniza-

tion and Bus Tail-off Adjustment. These are both described in

the following sections.

●

the data patterns being transmitted. Some repeating

data word values cause greater tail-off magnitude

than random data or other repeating data patterns.

For Holt transceivers, 32-word transmissions using

repeating 0x0000 data usually give worst case tail-off

magnitude

timing skew for TX and TX input signals generated by

the encoder

HOLT INTEGRATED CIRCUITS

●

HI-1585

FUNCTIONAL DESCRIPTION

Valid Transmit

Command From

Bus Controller

to Terminal

The Remote Terminal Transmits Response:

Status Word and Data Words

This Area of Interest is Magnified Below

Last midbit zero crossing

0 Volts

a) Ideal Waveform Has No Tail-off or Ringing

b) Exponentially-Decaying Positive Tail-off

c) Exponentially-Decaying Negative Tail-off

Figure 2. Transmit-induced Tail-off (Offset)

HOLT INTEGRATED CIRCUITS