July 2011
Single-Rail ARINC 429 Differential Line Driver
PIN CONFIGURATION (TOP VIEW)
AMPB 1
TXBOUT 2
TX0IN 3
TX1IN 4
CP- 5
CP+ 6
VDD2P 7
VDD 8
16 AMPA
15 TXAOUT
14 -
HI-8596
GENERAL DESCRIPTION
The HI-8596 bus interface product is a silicon gate
CMOS device designed as a line driver in accordance
with the ARINC 429 bus specifications. The part includes
a dual polarity voltage doubler, allowing it to operate
from a single +3.3V supply using only four external ca-
pacitors. The part also features high-impedance outputs
(tri-state) when both data inputs are taken high, allowing
multiple line drivers to be connected to a common bus.
Logic inputs feature built-in 4kV ESD input protection
(HBM) as well as 5V or 3.3V logic level compatibility.
37.5 Ohm or 5 Ohm resistors in series with each ARINC
output are available to allow the use of external resistors
for lightning protection.
The HI-8596 line driver is intended for use where logic
signals must be converted to ARINC 429 levels such
as when using an FPGA or the HI-3586 ARINC 429
protocol IC.
The part is available in Industrial -40 C to +85 C, or
o
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Extended, -55 C to +125 C temperature ranges. Optional
burn-in is available on the extended temperature range.
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HI-8596PSI
HI-8596PST
13 SLP
12 CN+
11 CN-
10 VDD2N
9 GND
16-Pin Plastic SOIC package
(Narrow Body)
(See
page 9 for additional package pin configurations)
Table 1. Function Table
TX1IN
0
0
0
1
1
1
TX0IN
0
1
1
0
0
1
SLP
X
0
1
0
1
X
TXAOUT
0V
-5V
-5V
5V
5V
Hi-Z
TXBOUT
0V
5V
5V
-5V
-5V
Hi-Z
SLOPE
N/A
10μs
1.5μs
10μs
1.5μs
N/A
FEATURES
• Single +3.3V supply
• All ARINC 429 voltage levels generated on-chip
• Digitally selectable rise and fall times
• Tri-state Outputs
• 5 Ohm or 37.5 Ohm output resistance
• Industrial and Extended temperature ranges
• Burn-in available
DS8596 Rev. B.
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07/11
HI-8596
BLOCK DIAGRAM
V
DD
C
SUPPLY
SLP
TX0IN
TX1IN
3.3V
5 OHMS
VDD2+
ONE
ESD
PROTECTION
& VOLTAGE
TRANSLATION
AMPA
TXAOUT
5V
CURRENT
CONTROL
“A” SIDE
NULL
ZERO
CONTROL
LOGIC
37.5 OHMS
-5V
VDD2-
ONE
NULL
5V
CURRENT
CONTROL
5 OHMS
AMPB
TXBOUT
“B” SIDE
37.5 OHMS
GND
V
DD
ZERO
CONTROL
LOGIC
-5V
VDD2+
CP+
C
FLY
CP-
CN+
C
FLY
CN-
Dual Polarity
Voltage Doubler
VDD2-
VDD2+
C
OUT
VDD2-
C
OUT
Figure 1. HI-8596 Block Diagram
HOLT INTEGRATED CIRCUITS
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HI-8596
PIN DESCRIPTIONS
Table 2. Pin Descriptions
Pin
SLP
TX0IN
TX1IN
V
DD
GND
V
DD2+
CP+
CP-
V
DD2-
CN+
CN-
TXAOUT
AMPA
TXBOUT
AMPB
Function
INPUT
INPUT
INPUT
POWER
POWER
OUTPUT
ANALOG
ANALOG
OUTPUT
ANALOG
ANALOG
OUTPUT
OUTPUT
OUTPUT
OUTPUT
Description
Output slew rate control. High selects ARINC 429 high-speed. Low selects
ARINC 429 low-speed.
Data input zero
Data input one
+3.3V power supply
Ground supply
Voltage doubler positive output (~6.6V for 3.3V supply)
V
DD2+
flyback capacitor, C
FLY
; positive terminal
V
DD2+
flyback capacitor, C
FLY
; negative terminal
Voltage doubler negative output (~ -6.6V for 3.3V supply)
V
DD2-
flyback capacitor, C
FLY
; positive terminal
V
DD2-
flyback capacitor, C
FLY
; negative terminal
ARINC high output with 37.5 Ohms series resistance
ARINC high output with 5 Ohms series resistance
ARINC low output with 37.5 Ohms series resistance
ARINC low output with 5 Ohms series resistance
HOLT INTEGRATED CIRCUITS
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HI-8596
FUNCTIONAL DESCRIPTION
Figure 1 is a block diagram of the line driver. The HI-8596
requires only a single +3.3V power supply. An integrated
inverting / non-inverting voltage doubler generates the
rail voltages (±6.6V) which are then used to produce the
±5V ARINC-429 output levels.
The internal dual polarity charge pump circuit requires
four external capacitors, two for each polarity gener-
ated by the doubler. CP+ and CP- connect the exter-
nal charge transfer or “fly” capacitor, C
FLY
, to the positive
portion of the doubler, resulting in twice V
DD
at the V
DD2+
pin. An output “hold” capacitor, C
OUT
, is placed between
V
DD2+
and GND. C
OUT
should be ten times the size of C
FLY
.
The inverting or negative portion of the converter works
in a similar fashion, with C
FLY
and C
OUT
placed between
CN+ / CN- and V
DD2-
/ GND respectively.
Currents for slope control are set by on-chip resistors.
The TX0IN and TX1IN inputs receive logic signals
from a control transmitter chip such as the HI-3584.
TXAOUT and TXBOUT hold each side of the ARINC bus
at Ground until one of the inputs becomes a One. If for
example TX1IN goes high, a charging path is enabled to
5V on an “A” side internal capacitor while the “B” side is
enabled to -5V. The charging current is selected by the
SLP pin. If the SLP pin is high, the capacitor is nominally
charged from 10% to 90% in 1.5μs. If SLP is low, the
rise and fall times are 10μs.
A unity gain buffer receives the internally generated
slopes and differentially drives the ARINC line. Cur-
rent is limited by the series output resistors at each pin.
There are no fuses at the outputs of the HI-8596.
The HI-8596 has 37.5 ohms in series with each TXOUT
output and 5 ohms in series with each AMP output. The
AMP outputs are for applications where external series
resistance is required, typically for lightning protection
devices. Holt Application Note AN-300 describes suit-
able lightning protection schemes.
Tri-stateable outputs allow multiple line drivers to be
connected to the same ARINC 429 bus. Setting TX1IN
and TX0IN both to a logic “1” puts the outputs in the
high-impedance state.
ABSOLUTE MAXIMUM RATINGS
Supply Voltages
Power Dissipation at 25 C
V
DD
.......................................................... +5V
o
RECOMMENDED OPERATING
CONDITIONS
Supply Voltages
Temperature Range
V
DD
................................... +3.0V to +3.6V
Industrial Screening .............. -40 C to +85 C
Hi-Temp Screening .............. -55 C to +125 C
NOTE: Stresses above absolute maximum ratings or outside recom-
mended operating conditions may cause permanent damage to the
device. These are stress ratings only. Operation at the limits is not
recommended.
o
o
o
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plastic SOIC ........... 1.0W, derate 10mW/ C
ceramic DIP ......... 0.5W, derate 7mW/ C
Solder Temperature ......................... 275 C for 10sec
Storage Temperature ....................... -65 C to +150 C
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o
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Note: HEAT SINK on QFN PACKAGE
The HI-8596 driver is available in a small-footprint, thermally
enhanced QFN (chip-scale) package. This package includes
an electrically isolated metal heat sink located on the bottom
surface of the device. This heat sink should be soldered down
to the printed circuit board for optimum thermal dissipation.
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HI-8596
ELECTRICAL CHARACTERISTICS
Table 3. DC Electrical Characteristics
V
DD
= +3.3V, T
A
= Operating Temperature Range (unless otherwise stated)
Parameters
Input Voltage (TX1IN, TX0IN, SLP)
High
Low
Input Current (TX1IN, TX0IN, SLP)
Source
Sink
ARINC Output Voltage (Differential)
one
zero
null
ARINC Output Voltage (Ref. to GND)
one or zero
null
Operating Supply Current
No load
Max. Load
ARINC Output Impedance
TXOUT pins
AMP pins
ARINC Output Tri-State Current
Symbol
V
IH
V
IL
I
IH
I
IL
V
DIFF1
V
DIFF0
V
DIFFN
V
DOUT
V
NOUT
I
DDNL
I
DDL
Z
OUT
Test Conditions
Min
0.7V
DD
-
Typ
-
-
-
45
10
-10
0
5.0
0
28
65
37.5
5
Max
-
0.3V
DD
0.1
Units
V
V
μA
μA
V
IN
= 0V
V
IN
= 3.3V, 7.34kΩ pulldown
no load; TXAOUT - TXBOUT
no load; TXAOUT - TXBOUT
no load; TXAOUT - TXBOUT
no load & magnitude at pin
no load
SLP = V
DD
TX1IN & TX0IN = 0V
100kHz, 400Ω load
-
-
9
-11
-0.5
4.5
-0.25
-
-
11
-9
0.5
5.5
0.25
40
-
V
V
V
V
V
mA
mA
Ohms
Ohms
I
OZ
TX0IN = TX1IN = V
DD
-5.75V < V
OUT
< +5.75V
-1.0
0
+1.0
μA
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