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HI7191
Data Sheet
June 1, 2006
FN4138.8
24-Bit, High Precision, Sigma Delta A/D
Converter
The Intersil HI7191 is a monolithic instrumentation, sigma
delta A/D converter which operates from
±5V
supplies. Both
the signal and reference inputs are fully differential for
maximum flexibility and performance. An internal
Programmable Gain Instrumentation Amplifier (PGIA)
provides input gains from 1 to 128 eliminating the need for
external pre-amplifiers. The on-demand converter
auto-calibrate function is capable of removing offset and gain
errors existing in external and internal circuitry. The on-board
user programmable digital filter provides over 120dB of
60/50Hz noise rejection and allows fine tuning of resolution
and conversion speed over a wide dynamic range. The
HI7190 and HI7191 are functionally the same device, but the
HI7190 has tighter linearity specs.
The HI7191 contains a serial I/O port and is compatible with
most synchronous transfer formats including both the
Motorola 6805/11 series SPI and Intel 8051 series SSR
protocols. A sophisticated set of commands gives the user
control over calibration, PGIA gain, device selection, standby
mode, and several other features. The On-chip Calibration
Registers allow the user to read and write calibration data.
Features
• 20-Bit Resolution with No Missing Code
• 0.0015% Integral Non-Linearity (Typ)
• 20mV to
±2.5V
Full Scale Input Ranges
• Internal PGIA with Gains of 1 to 128
• Serial Data I/O Interface, SPI Compatible
• Differential Analog and Reference Inputs
• Internal or System Calibration
• 120dB Rejection of 60/50Hz Line Noise
• Settling Time of 4 Conversions (Max) for a Step Input
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Process Control and Measurement
• Industrial Weight Scales
• Part Counting Scales
• Laboratory Instrumentation
• Seismic Monitoring
• Magnetic Field Monitoring
Ordering Information
PART
NUMBER
HI7191IP
HI7191IPZ
(See Note)
HI7191IB
HI7191IBZ
(See Note)
PART
MARKING
HI7191IP
HI7191IPZ
HI7191IB
HI7191IBZ
TEMP.
RANGE
(°C)
PACKAGE
PKG.
DWG. #
E20.3
E20.3
M20.3
M20.3
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• TB348 “HI7190/1 Negative Full Scale Error vs
Conversion Frequency”
• AN9504 “A Brief Intro to Sigma Delta Conversion”
• TB329 “Intersil Sigma Delta Calibration Technique”
• AN9505 “Using the HI7190 Evaluation Kit”
• TB331 “Using the HI7190 Serial Interface”
• AN9527 “Interfacing HI7190 to a Microcontroller”
• AN9532 “Using HI7190 in a Multiplexed System”
• AN9601 “Using HI7190 with a Single +5V Supply”
-40 to 85 20 Ld PDIP
-40 to 85 20 Ld PDIP*
(Pb-free)
-40 to 85 20 Ld SOIC
-40 to 85 20 Ld SOIC
(Pb-free)
HI7191IBZ-T HI7191IBZ
(See Note)
HI7190EVAL Evaluation Kit
M20.3
-40 to 85 20 Ld SOIC
Tape and Reel
(Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003, 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HI7191
Pinout
HI7191 (PDIP, SOIC)
TOP VIEW
SCLK
SDO
SDIO
CS
DRDY
DGND
AV
SS
V
RLO
V
RHI
1
2
3
4
5
6
7
8
9
20 MODE
19 SYNC
18 RESET
17 OSC
1
16 OSC
2
15 DV
DD
14 AGND
13 AV
DD
12 V
INHI
11 V
INLO
V
CM
10
Functional Block Diagram
V
RHI
AV
DD
TRANSDUCER
BURN-OUT
CURRENT
V
RLO
REFERENCE
INPUTS
∑−Δ
MODULATOR
V
INHI
V
INLO
PGIA
∑
∫
∑
∫
1-BIT
D/A
DIGITAL FILTER
1
V
CM
CONTROL AND SERIAL INTERFACE UNIT
SERIAL INTERFACE
UNIT
CLOCK
GENERATOR
CONTROL REGISTER
OSC
1
OSC
2
DRDY RESET SYNC
CS
MODE
S
CLK
SDIO
SDO
2
FN4138.8
June 1, 2006
HI7191
Typical Application Schematic
10MHz
17
+5V
13
+
0.1μF
INPUT
INPUT
+
-
R
1
12
11
10
V
INHI
V
INLO
V
CM
SCLK
SDIO
SDO
SYNC
+2.5V
REFERENCE
9
8
7
+
0.1μF
4.7μF
AGND
14
V
RHI
V
RLO
AV
SS
CS
DRDY
RESET
MODE
DGND
6
20
4
CS
5
18
DRDY
RESET
4.7μF
0.1μF
1
3
2
19
SYNC
DATA I/O
DATA OUT
AV
DD
16
15
DV
DD
+
4.7μF
+5V
OSC
1
OSC
2
-5V
3
FN4138.8
June 1, 2006
HI7191
Absolute Maximum Ratings
Supply Voltage
AV
DD
to AGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V
AV
SS
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5.5V
DV
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±0.3V
Analog Input Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . AV
SS
to AV
DD
Digital Input, Output and I/O Pins . . . . . . . . . . . . . . DGND to DV
DD
ESD Tolerance (No Damage)
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500V
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+100V
Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1000V
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(°C/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
125
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
Maximum Junction Temperature
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering, 10s). . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER
SYSTEM PERFORMANCE
Integral Non-Linearity, INL
Differential Non-Linearity
Offset Error, V
OS
Offset Error Drift
Full Scale Error, FSE
Noise, e
N
AV
DD
= +5V, AV
SS
= -5V, DV
DD
= +5V, V
RHI
= +2.5V, V
RLO
= AGND = 0V, V
CM
= AGND,
PGIA Gain = 1, OSC
IN
= 10MHz, Bipolar Input Range Selected, f
N
= 10Hz
TEST CONDITIONS
MIN
TYP
±0.0015
MAX
±0.003
UNITS
End Point Line Method (Notes 3, 5, 6)
(Note 2)
(See Table 1)
V
INHI
= V
INLO
(Notes 3, 8)
V
INHI
- V
INLO
= +2.5V (Notes 3, 5, 8, 10)
(See Table 1)
V
CM
= 0V, V
INHI
= V
INLO
from -2V to +2V
Filter Notch = 10Hz, 25Hz, 50Hz (Note 2)
Filter Notch = 10Hz, 30Hz, 60Hz (Note 2)
-
%FS
LSB
-
μV/
°C
-
-
dB
dB
dB
Conversions
No Missing codes to 20-Bits
-
-
-
-
-
120
120
-
-
1
-
-
70
-
-
2
-
-
-
-
-
-
-
4
Common Mode Rejection Ratio, CMRR
Normal Mode 50Hz Rejection
Normal Mode 60Hz Rejection
Step Response Settling Time
ANALOG INPUTS
Input Voltage Range
Input Voltage Range
Common Mode Input Range
Input Leakage Current, I
IN
Input Capacitance, C
IN
Reference Voltage Range, V
REF
(V
REF
= V
RHI
- V
RLO
)
Transducer Burn-Out Current, I
BO
CALIBRATION LIMITS
Positive Full Scale Calibration Limit
Negative Full Scale Calibration Limit
Offset Calibration Limit
Input Span
DIGITAL INPUTS
Input Logic High Voltage, V
IH
Input Logic Low Voltage, V
IL
Unipolar Mode (Note 9)
Bipolar Mode (Note 9)
(Note 2)
V
IN
= AV
DD
(Note 2)
0
- V
REF
AV
SS
-
-
2.5
-
-
-
-
-
5.0
-
200
V
REF
V
REF
AV
DD
1.0
-
5
-
V
V
V
nA
pF
V
nA
-
-
-
0.2(V
REF
/Gain)
(Note 11)
2.0
-
-
-
-
-
1.2(V
REF
/Gain)
1.2(V
REF
/Gain)
1.2(V
REF
/Gain)
2.4(V
REF
/Gain)
-
0.8
-
-
-
-
-
-
V
V
4
FN4138.8
June 1, 2006
