HIP6301V, HIP6302V
NOT RECOMMENDED FOR NEW DESIGNS
NO RECOMMENDED REPLACEMENT
contact our Technical Support Center at
1-888-INTERSIL or www.intersil.com/tsc
DATASHEET
FN9034
Rev 3.00
May 5, 2008
Microprocessor CORE Voltage Regulator Multi-Phase Buck PWM Controller
The HIP6301V and HIP6302V control microprocessor
CORE voltage regulation by driving up to four
synchronous-rectified buck channels in parallel. Multiphase
buck converter architecture uses interleaved timing to
multiply ripple frequency and reduce input and output ripple
currents. Lower ripple results in fewer components, lower
component cost, reduced power dissipation, and a smaller
implementation area. The HIP6301V is a versatile 2- to
4-phase controller and the HIP6302V is a cost-saving
dedicated 2-phase controller.
The HIP6301V and HIP6302V are exact pin compatible
replacements for their predecessor parts, the HIP6301 and
HIP6302. They are the first controllers to incorporate
Dynamic VID™ technology to manage the output voltage
and current during on-the-fly DAC changes. Using Dynamic
VID, the HIP6301V and HIP6302V detect changes in the
VID code, and gradually change the reference in 25mV
increments until reaching the new value. By gradually
changing the reference setting, in-rush current and the
accompanying voltage swings remain negligibly small.
Intersil offers a wide range of MOSFET drivers to form highly
integrated solutions for high-current, high slew-rate
applications. The HIP6301V and HIP6302V regulate output
voltage, balance load currents and provide protective
functions for two to four synchronous-rectified buck
converter channels. These parts feature an integrated
high-bandwidth error amplifier for fast, precise regulation
and a 5-bit DAC for the digital interface to program the 0.8%
accuracy. A window comparator toggles PGOOD if the
output voltage moves out of range, and acts to protect the
load in case of over voltage.
Current sensing is accomplished by reading the voltage
developed across the lower MOSFETs during their
conduction intervals. Current sensing provides the needed
signals for precision droop, channel-current balancing, load
sharing, and overcurrent protection. This saves cost by
taking advantage of the power device’s parasitic on
resistance.
Features
• Multi-Phase Power Conversion
• Precision CORE Voltage Regulation
- ±0.8% System Accuracy Over-Temperature
• Microprocessor Voltage Identification Input
- Dynamic-VID Technology
- 5-bit VID Decoder
• Precision Channel-Current Balance
• Overcurrent Protection
• Lossless Current Sensing
• Programmable “Droop” Voltage
• Fast Transient Response
• Selection of 2-, 3-, or 4-Phase Operation
• High Ripple Frequency (100kHz to 6MHz)
• Pb-Free Available (RoHS Compliant)
Ordering Information
PART
NUMBER
HIP6301VCB*
HIP6301VCBZ*
(Note)
PART
MARKING
HIP6301VCB
HIP6301VCBZ
TEMP.
RANGE
(°C)
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
PKG.
DWG. #
M20.3
M20.3
M20.3
M16.15
M16.15
PACKAGE
20 Ld SOIC
20 Ld SOIC
(Pb-free)
20 Ld SOIC
(Pb-free)
16 Ld SOIC
16 Ld SOIC
(Pb-free)
HIP6301VCBZA* HIP6301VCBZ
(Note)
HIP6302VCB*
HIP6302VCBZ*
(Note)
HIP6302VCB
HIP6302VCBZ
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on
reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach materials
and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which
is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at Pb-
free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
FN9034 Rev 3.00
May 5, 2008
Page 1 of 20
HIP6301V, HIP6302V
Pinouts
HIP6301V
(20 LD SOIC
TOP VIEW
VID4 1
VID3 2
VID2 3
VID1 4
VID0 5
COMP 6
FB 7
FS/DIS 8
GND 9
VSEN 10
20 V
CC
19 PGOOD
18 PWM4
17 ISEN4
16 ISEN1
15 PWM1
14 PWM2
13 ISEN2
12 ISEN3
11 PWM3
VID4 1
VID3 2
VID2 3
VID1 4
VID0 5
COMP 6
FB 7
FS/DIS 8
HIP6302V
(16 LD SOIC
TOP VIEW
16 V
CC
15 PGOOD
14 ISEN1
13 PWM1
12 PWM2
11 ISEN2
10 VSEN
9 GND
FN9034 Rev 3.00
May 5, 2008
Page 2 of 20
HIP6301V, HIP6302V
HIP6301V Block Diagram
PGOOD
VCC
POWER-ON
RESET (POR)
VSEN
X 0.9
+
UV
-
S
+
OV
X1.15
-
OV
LATCH
THREE-STATE
CLOCK AND
SAWTOOTH
GENERATOR
+
FS/DIS
-
+
PWM
-
PWM1
SOFT-
START
AND FAULT
LOGIC
+
-
+
PWM
-
PWM2
COMP
+
-
+
PWM
-
PWM3
VID0
VID1
VID2
VID3
VID4
DYNAMIC
VID
D/A
+
+
E/A
-
-
+
PWM
-
PWM4
FB
CURRENT
CORRECTION
PHASE
NUMBER
CHANNEL
DETECTOR
ISEN1
I_TOT
-
OC
+
I_TRIP
+
ISEN2
ISEN3
+
+
+
ISEN4
GND
FN9034 Rev 3.00
May 5, 2008
Page 3 of 20
HIP6301V, HIP6302V
HIP6302V Block Diagram
PGOOD
VCC
POWER-ON
RESET (POR)
VSEN
X 0.9
+
UV
-
S
+
OV
X1.15
-
OV
LATCH
TRI-STATE
CLOCK AND
SAWTOOTH
GENERATOR
+
FS/DIS
-
+
PWM
-
PWM1
SOFT-
START
AND FAULT
LOGIC
COMP
+
VID0
VID1
VID2
VID3
VID4
DYNAMIC
VID
D/A
-
+
PWM
-
PWM2
+
E/A
-
FB
CURRENT
CORRECTION
I_TOT
-
OC
+
I_TRIP
ISEN1
+
+
ISEN2
GND
FN9034 Rev 3.00
May 5, 2008
Page 4 of 20
HIP6301V, HIP6302V
HIP6301V and HIP6302V Functional Pin Descriptions
HIP6301V
(20 LD SOIC
TOP VIEW
VID4 1
VID3 2
VID2 3
VID1 4
VID0 5
COMP 6
FB 7
FS/DIS 8
GND 9
VSEN 10
20 V
CC
19 PGOOD
18 PWM4
17 ISEN4
16 ISEN1
15 PWM1
14 PWM2
13 ISEN2
12 ISEN3
11 PWM3
VID4 1
VID3 2
VID2 3
VID1 4
VID0 5
COMP 6
FB 7
FS/DIS 8
HIP6302V
(16 LD SOIC
TOP VIEW
16 V
CC
15 PGOOD
14 ISEN1
13 PWM1
12 PWM2
11 ISEN2
10 VSEN
9 GND
VID4, VID3, VID2, VID1 and VID0
(Pins 1 thru 5 - Both Parts)
Voltage Identification inputs. The HIP6301V and HIP6302V
decode the VID bits to establish the reference voltage (see
Table 1). Each pin has an internal 20µA pull-up current source
to 2.5V making the parts compatible with CMOS and TTL
logic from 5V down to 2.5V. When a VID change is detected,
the reference voltage slowly ramps up or down to the new
value in 25mV steps. VID input levels above 2.9V may
produce an reference-voltage offset inaccuracy.
PWM1 (Pin 15 - HIP6301V, Pin 13 - HIP6302V),
PWM2 (Pin 14 - HIP6301V, Pin 12 - HIP6302V),
PWM3 (Pin 11 - HIP6301V only) and PWM4
(Pin 18 - HIP6301V only)
PWM outputs for each channel. Connect these pins to the
PWM input of the external MOSFET driver. For HIP6301V
systems using 3 channels, connect PWM4 high. For two
channel systems, connect PWM3 and PWM4 high.
COMP (Pin 6 - Both Parts)
Output of the internal error amplifier. Connect this pin to the
external feedback and compensation network.
ISEN1 (Pin 16 - HIP6301V, Pin 14 - HIP6302V),
ISEN2 (Pin 13 - HIP6301V, Pin 11 - HIP6302V),
ISEN3 (Pin 12 - HIP6301V only) and ISEN4
(Pin 17 - HIP6301V only)
Current sense inputs from the individual converter channel’s
phase nodes. Unused sense lines MUST be left open.
FB (Pin 7 - Both Parts)
Inverting input of the internal error amplifier.
PGOOD (Pin 19 - HIP6301V, Pin 15 - HIP6302V)
Power-good. This pin is an open-drain logic signal that
indicates when the microprocessor CORE voltage (VSEN
pin) is within specified limits and soft-start has timed out.
FS/DIS (Pin 8 - Both Parts)
Channel frequency, F
SW
, select and disable. A resistor from
this pin to ground sets the switching frequency of the
converter. Pulling this pin to ground disables the converter
and three states the PWM outputs. See Figure 10.
V
CC
(Pin 20 - HIP6301V, Pin 16 - HIP6302V)
Bias supply. Connect this pin to a 5V supply.
GND (Pin 9 - Both Parts)
Bias and reference ground. All signals are referenced to this
pin.
VSEN (Pin 10 - Both Parts)
Power-good monitor input. Connect to the microprocessor CORE
voltage.
FN9034 Rev 3.00
May 5, 2008
Page 5 of 20
