HIP9010
TM
Data Sheet
November 1998
FN3601.4
Engine Knock Signal Processor
The HIP9010 is used to provide a method of detecting
premature detonation or “Knock” in automotive engines.
A block diagram of this IC is shown in Figure 1. The chip
alternately selects one of the two sensors mounted on the
engine block. Two programmable bandpass filters process
the signal from both sensors, and divides the signal into two
channels. When the engine is not knocking, programmable
gain adjust stages are set to ensure that both the reference
channel and the knock channel contain similar energies.
This technique ensures that the detection system is
comparatively immune to changes in the engine background
noise level. When the engine is knocking, the energy in the
knock channel increases.
Features
• Two Sensor Inputs
• Microprocessor Programmable
• Accurate and Stable Filter Elements
• Digitally Programmable Gain
• Digitally Programmable Time Constants
• Digitally Programmable Filter Characteristics
• On-Chip Clock
• Operating Temperature Range -40
o
C to 125
o
C
Applications
• Engine Knock Detector Processor
• Analog Signal Processing where Controllable Filter
Characteristics are Required
Ordering Information
PART NUMBER
HIP9010AB
TEMP.
RANGE (
o
C)
-40 to 125
PACKAGE
20 Ld SOIC (W)
PKG.
NO.
M20.3
Pinout
HIP9010
(SOIC)
TOP VIEW
V
DD
GND
V
MID
INOUT
NC
NC
INT/HOLD
CS
OSCIN
1
2
3
4
5
6
7
8
9
20 S0IN
19 S0FB
18 S1FB
17 S1IN
16 NC
15 NC
14 TEST
13 SCK
12 MOSI
11 MISO
OSCOUT 10
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
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Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
Simplified Block Diagram
REFERENCE FREQUENCY CHANNEL
2
(19) S0FB
(20) S0IN
PROGRAMMABLE
BANDPASS
FILTER
1-20kHz
64 STEPS
PROGRAMMABLE
GAIN
STAGE
1-0.133
64 STEPS
ACTIVE
FULL WAVE
RECTIFIER
DIFFERENTIAL
TO
SINGLE-ENDED
CONVERTER
AND OUTPUT
DRIVER
INOUT (4)
-
CHANNEL SELECT
SWITCHES
+
3RD ORDER
ANTIALIASING FILTER
(18) S1FB
PROGRAMMABLE
INTEGRATOR
40-600µs
32 STEPS
HIP9010
(17) S1IN
-
+
POWER SUPPLY
AND
BIAS CIRCUITS
PROGRAMMABLE
BANDPASS
FILTER
1-20kHz
64 STEPS
PROGRAMMABLE
STAGE
GAIN
1-0.133
64 STEPS
OSCIN (9)
ACTIVE
FULL WAVE
RECTIFIER
CLOCK
TO SWITCHED
CAPACITOR
NETWORKS
OSCOUT (10)
SCK (13)
CS (8)
KNOCK FREQUENCY CHANNEL
REGISTERS
AND
STATE MACHINE
(14) TEST
SPI
INTERSPACE
MOSI (12)
MISO (11)
INT/HOLD (7)
(3) V
MID
(1) V
DD
(2) GND
FIGURE 1.
HIP9010
Absolute Maximum Ratings
DC Logic Supply, V
DD
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
Output Voltage, V
O
. . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
Input Voltage, V
IN
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7V (Max)
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(
o
C/W)
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -40
o
C to 125
o
C
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
115
o
C to 150
o
C
Maximum Storage Temperature Range, T
STG
. . . . -65
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Lead Temperature (Soldering) . . . . . . . . . . . . . . . 300
o
C
At distance 1/16in
±
1/32in (1.59mm
±
0.79mm) from case
for 10s (Max) (SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
V
DD
= 5V,
±5%,
GND = 0V, Clock Frequency 4MHz,
±0.5%,
T
A
= -40
o
C to 125
o
C,
Unless Otherwise Specified
PARAMETER
DC ELECTRICAL CHARACTERISTICS
Quiescent Supply Current
Midpoint Voltage, Pin 3
Midpoint Voltage, Pin 3
Input Leakage, Pin 14
Internal Pull-Up Resistance, Pin 14
Leakage of Pins 7, 8, 12 and 13
Low Input Voltage, Pins 7, 8, 12 and 13
High Input Voltage, Pins 7, 8, 12 and 13
Low Level Output, Pin 11
Leakage Pin 11
Low Level Output, Pin 10
High Level Output, Pin 10
INPUT AMPLIFIERS
S0FB and S1FB High Output Voltage
S0FB and S1FB Low Output Voltage
S0FB and S1FB Closed Loop
S0FB and S1FB Closed Loop
ANTIALIASING FILTER
Response 1kHz to 20kHz,
Referenced to 1kHz
Attenuation at 180kHz
Referenced to 1kHz
PROGRAMMABLE FILTERS
Peak to Peak Voltage Output
Filters Q (Note 2)
PROGRAMMABLE GAIN AMPLIFIERS
Percent Amplifier Gain Deviation
Per Table 2
%G
Run Mode
-
±1
-
%
V
OUTP-P
Q
Run Mode
Run Mode
3.5
-
4.0
2.5
-
-
V
P-P
Q
BW
ATEN
Test Mode, 70mV
RMS
Input to S0FB or
S1FB, Output Pin 4
Test Mode, 70mV
RMS
Input to S0FB or
S1FB, Output Pin 4
-
-10
-2
-15
-
-
dB
dB
V
OUT
HI
V
OUT
LO
A
CL
A
CL
100µA I
SINK
, V
DD
= 5V
100µA I
SOURCE
, V
DD
= 5V
Input Resistor = 1MΩ,
Feedback Resistor = 49.9kΩ
Input Resistor = 47.5kΩ,
Feedback Resistor = 475kΩ
4.7
-
-25
18
4.9
15
-26
20
-
200
-27
21
V
mV
dB
dB
I
DD
V
MID
V
MID
IL
TEST
R
TEST
I
L
V
IL
V
IH
V
OL
I
L
V
OL
V
OH
I
SOURCE
= 4mA
Measured at GND and V
DD
= 5V
I
SOURCE
= 500µA, V
DD
= 5V
I
SINK
= -500µA, V
DD
= 5V
V
DD
= 5.25V, GND = 0V
V
DD
= 5.0V, I
L
= 2mA Source
V
DD
= 5.0V, I
L
= 0mA
Measured at V
DD
= 5.0V
V
DD
= 5.0V, I Measure = 15µA
Measured at GND and V
DD
= 5V
3
2.3
2.4
-
30
-
-
70
0.01
-
-
4.4
7.5
2.45
2.5
-
100
-
-
-
-
-
-
-
12
2.55
2.6
3
200
±
3
30
-
0.30
±10
1.5
-
mA
V
V
µA
KΩ
µA
% of V
DD
% of V
DD
V
µA
V
V
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
3
HIP9010
Electrical Specifications
V
DD
= 5V,
±5%,
GND = 0V, Clock Frequency 4MHz,
±0.5%,
T
A
= -40
o
C to 125
o
C,
Unless Otherwise Specified
(Continued)
PARAMETER
INTEGRATOR
Integrator Offset Voltage
Integrator Reset Voltage
Integrator Droop after 500µs
OUTPUT AND SAMPLE AND HOLD
Differential to Single Ended
Converter Offset Voltage
Change in Converter Output
SYSTEM GAIN DEVIATION
Gain Deviation from “Ideal Equation”
Correlation, Factor - 5.0%
V
OUT
-
V
RESET
Run Mode, maximum signal output
from Input Amplifier <2.25V
P-P
,
Equation Output x 0.95 + Device
Reset Voltage. For Total V
OUT
≤
4.7V
-8%,
±±100mV
Equation
x 0.95
-V
RESET
8%,
±100mV
V
DIFV
IO
DIFOUT
By Design
Run Mode, 500µA, Sinking to No Load
-
-
0.1
±±1
-
±±3
mV
mV
INTGV
IO
V
RESET
V
DROOP
By Design
Pin 4 Voltage at Initiation of
Integration Cycle. V
DD
= 5V
Hold Mode, Pin 7 = 0V, V
DD
= 5V,
Pin 4 set to 20% to 80% of V
DD
-
430
-
0.1
500
±±3
-
570
±±50
mV
mV
mV
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
NOTE:
2. Q = f
O
/BW, Where: f
O
= Center Frequency, BW = 3dB bandwidth.
Ideal Equation
R
F
INTO UT
(
volts
)
=
Input signal (V
P
–
P
) ×
---------
-
R
IN
N
N
-
-
G
K
×
1.273
×
-------------------------------------------------- –
G
R
×
1.273
×
--------------------------------------------------
TC (ms)
×
f
Q
(kHz)
TC (ms)
×
f
Q
(kHz)
+
V
R ESET
When the two filters are set to the same frequency and the input signal is present for the periods T
IN
, then:
R
F
INTO UT
(
volts
)
=
Input signal (V
P
–
P
) ×
---------
-
R
IN
T
I N
-
1.273
×
--------
(
G
K
–
G
R
)
TC
+
V
RESET
G
R
and G
K
= Programed Gain of Reference and Knock channels.
T
IN
= Time input signal is present In ms.
T
C
= Programmed integrator time constant ms.
N = Number of cycles of input signal.
f
Q
= Frequency of input signal. Assumes both filters are programmed to the same frequency.
V
RESET
= Integrator Reset Voltage.
1.273 = 4/π
R
F
= Feedback resistor value.
R
IN
= Signal input resistor value.
For example, assume 300mV
P-P
input with the time constant programmed to 300µs and the Integration time is 1.2ms. The R
F
/R
IN
ratio is one and
the Reference channel is programmed to a Gain of 0.188. The Knock channel is then automatically set to a gain of one. The input signal is contin-
uous for the total integration time, T
IN
.
INTO UT
(
volts
)
=
0.3V (V
P
–
P
) ×
1.2ms
1.273
×
-----------------------
× (
1.000
–
0.188
)
0.300m s
+
V
RESET
=
1.24 V
+
0.500V
=
1.74V
4
HIP9010
+5V
C3, 0.022µF
GND
MOSI
C2, 3.3nF
S1IN
R2
C1, 3.3nF
R1
TRANSDUCERS
20pF
4MHz
OSCOUT
20pF
1M
A/D
CONVERTER
INTOUT
R3
OSCIN
R4
S0IN
S0FB
TEST
S1FB
MISO
SCK
CS
INT/HOLD
SPI BUS
V
DD
V
MID
HIP9010
MICROPROCESSOR
FIGURE 2. SIMPLIFIED BLOCK DIAGRAM OF THE HIP9010 IN AN AUTOMOTIVE APPLICATION
Pin Descriptions
PIN
NUMBER
1
2
3
4
5 and 6
7
8
9
10
11
12
13
14
15 and 16
17
18
19
20
SYMBOL
V
DD
GND
V
MID
INTOUT
NC
INT/HOLD
CS
OSCIN
OSCOUT
MISO
MOSI
SCK
TEST
NC
S1IN
S1FB
S0FB
S0IN
5V power input.
This terminal is tied to ground.
This terminal is tied to the internal mid-supply generator and is brought out for supply bypassing by a 0.022µF
capacitor.
Buffered output of the integrator.
These terminals are not internally connected. DO NOT USE.
Selects whether the chip is in the Integrate Mode (Input High) or in the Hold Mode (Input Low).
A low input on this pin enables the chip to communicate over the SPI bus.
Input to inverter used for the oscillator circuit. A 4MHz crystal or ceramic resonator is connected between this
pin and pin 10. To bias the inverter, a 1.0MΩ to 10MΩ resistor is usually connected between this pin and pin 10.
Output of the inverter used for the oscillator. See pin 9 above.
Output of the chip SPI data bus. It is the inversion of the chip DATAIN line. This is an open drain output. The
output must be disabled by placing the CS High when the chip is not selected.
Input of the chip SPI data bus. Data length is eight bits.
Input from the SPI clock. Normally high, the data is clocked to the chip internal circuitry on the rising clock edge.
A low on this pin places the chip in the test mode. For normal operation this terminal is tied high or left open.
These terminals are not internally connected. DO NOT USE.
Inverting input to sensor one amplifier. A resistor is tied from this summing input to the transducer. A second
resistor is tied between this terminal and terminal 18, S1FB to establish the gain of the amplifier.
Output of the sensor one amplifier. This terminal is used to apply feedback.
Output of the sensor zero amplifier. This terminal is used to apply feedback.
Inverting input to sensor zero amplifier. A resistor is tied from this summing input to the transducer. A second
resistor is tied between this terminal and terminal 19, S0FB to establish the gain of the amplifier.
DESCRIPTION
5
