HM5164805 Series
HM5165805 Series
64 M EDO DRAM (8-Mword
×
8-bit)
8 k Refresh/4 k Refresh
ADE-203-808B (Z)
Rev. 1.0
Feb. 27, 1998
Description
The Hitachi HM5164805 Series, HM5165805 Series are 64M-bit dynamic RAMs organized as 8,388,608-
word
×
8-bit. They have realized high performance and low power by employing CMOS process
technology. HM5164805 Series, HM5165805 Series offer Extended Data Out (EDO) Page Mode as a
high speed access mode. They have the package variation of standard 32-pin plastic SOJ and standard
32-pin plastic TSOPII.
Features
•
Single 3.3 V supply: 3.3 V ± 0.3 V
•
Access time: 50 ns/60 ns (max)
•
Power dissipation
Active: 414 mW/378 mW (max) (HM5164805 Series)
: 486 mW/414 mW (max) (HM5165805 Series)
Standby : 1.8 mW (max) (CMOS interface)
: 0.54 mW (max) (L-version)
•
EDO page mode capability
•
Refresh cycles
#$
-only refresh
8192 cycles
/64 ms (HM5164805)
/128 ms (HM5164805L) (L-version)
4096 cycles
/64 ms (HM5165805)
/128 ms (HM5165805L) (L-version)
HM5164805 Series, HM5165805 Series
CBR/Hidden refresh
4096 cycles
/64 ms (HM5164805, HM5165805)
/128 ms (HM5164805L, HM5165805L) (L-version)
•
4 variations of refresh
#$
-only refresh
$
-before-
#$
refresh
Hidden refresh
Self refresh (L-version)
•
Battery backup operation (L-version)
Ordering Information
Type No.
HM5164805J-5
HM5164805J-6
HM5164805LJ-5
HM5164805LJ-6
HM5165805J-5
HM5165805J-6
HM5165805LJ-5
HM5165805LJ-6
HM5164805TT-5
HM5164805TT-6
HM5164805LTT-5
HM5164805LTT-6
HM5165805TT-5
HM5165805TT-6
HM5165805LTT-5
HM5165805LTT-6
Access time
50 ns
60 ns
50 ns
60 ns
50 ns
60 ns
50 ns
60 ns
50 ns
60 ns
50 ns
60 ns
50 ns
60 ns
50 ns
60 ns
400-mil 32-pin plastic TSOP II
(TTP-32DC)
Package
400-mil 32-pin plastic SOJ
(CP-32DC)
2
HM5164805 Series, HM5165805 Series
Pin Arrangement
(HM5164805 Series)
32-pin SOJ
32-pin TSOP
V
CC
I/O0
I/O1
I/O2
I/O3
NC
V
CC
WE
RAS
A0
A1
A2
A3
A4
A5
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
SS
I/O7
I/O6
I/O5
I/O4
V
SS
CAS
OE
A12
A11
A10
A9
A8
A7
A6
V
SS
V
CC
I/O0
I/O1
I/O2
I/O3
NC
V
CC
WE
RAS
A0
A1
A2
A3
A4
A5
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
SS
I/O7
I/O6
I/O5
I/O4
V
SS
CAS
OE
A12
A11
A10
A9
A8
A7
A6
V
SS
(Top view)
(Top view)
Pin Description
Pin name
A0 to A12
Function
Address input
•
•
I/O0 to I/O7
Row/Refresh address
Column address
A0 to A12
A0 to A9
Data input/output
Row address strobe
Column address strobe
Write enable
Output enable
Power supply
Ground
No connection
5$6
&$6
:(
2(
V
CC
V
SS
NC
3
HM5164805 Series, HM5165805 Series
Pin Arrangement
(HM5165805 Series)
32-pin SOJ
32-pin TSOP
V
CC
I/O0
I/O1
I/O2
I/O3
NC
V
CC
WE
RAS
A0
A1
A2
A3
A4
A5
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
SS
I/O7
I/O6
I/O5
I/O4
V
SS
CAS
OE
NC
A11
A10
A9
A8
A7
A6
V
SS
V
CC
I/O0
I/O1
I/O2
I/O3
NC
V
CC
WE
RAS
A0
A1
A2
A3
A4
A5
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
SS
I/O7
I/O6
I/O5
I/O4
V
SS
CAS
OE
NC
A11
A10
A9
A8
A7
A6
V
SS
(Top view)
(Top view)
Pin Description
Pin name
A0 to A11
Function
Address input
•
•
I/O0 to I/O7
Row/Refresh address
Column address
A0 to A11
A0 to A10
Data input/output
Row address strobe
Column address strobe
Write enable
Output enable
Power supply
Ground
No connection
5$6
&$6
:(
2(
V
CC
V
SS
NC
4
HM5164805 Series, HM5165805 Series
Block Diagram
(HM5164805 Series)
RAS
CAS
WE
OE
Timing and control
A0
A1
to
A9
Row decoder
Column decoder
Column
•
•
•
address
buffers
8M array
8M array
8M array
8M array
8M array
8M array
8M array
I/O buffers
I/O0
to
I/O7
8M array
•
•
•
Row
address
buffers
A10
to
A12
5
