HM62V8512B Series
4 M SRAM (512-kword
×
8-bit)
ADE-203-905G (Z)
Rev. 6.0
Mar. 31, 2000
Description
The Hitachi HM62V8512B is a 4-Mbit static RAM organized 512-kword
×
8-bit. It realizes higher density,
higher performance and low power consumption by employing 0.35
µm
Hi-CMOS process technology. The
device, packaged in a 525-mil SOP (foot print pitch width) or 400-mil TSOP TYPE II is available for high
density mounting. The HM62V8512B is suitable for battery backup system.
Features
•
Single 3.0 V supply: 2.7 V to 3.6 V
•
Access time: 70/85 ns (max)
•
Power dissipation
Active: 15 mW/MHz (typ)
Standby: 3
µW
(typ)
•
Completely static memory. No clock or timing strobe required
•
Equal access and cycle times
•
Common data input and output: Three state output
•
Directly LV-TTL compatible: All inputs
•
Battery backup operation
HM62V8512B Series
Ordering Information
Type No.
HM62V8512BLFP-7
HM62V8512BLFP-8
HM62V8512BLFP-7SL
HM62V8512BLFP-8SL
HM62V8512BLFP-7UL
HM62V8512BLFP-8UL
HM62V8512BLTT-7
HM62V8512BLTT-8
HM62V8512BLTT-7SL
HM62V8512BLTT-8SL
HM62V8512BLTT-7UL
HM62V8512BLTT-8UL
HM62V8512BLRR-7
HM62V8512BLRR-8
HM62V8512BLRR-7SL
HM62V8512BLRR-8SL
HM62V8512BLRR-7UL
HM62V8512BLRR-8UL
Access time
70 ns
85 ns
70 ns
85 ns
70 ns
85 ns
70 ns
85 ns
70 ns
85 ns
70 ns
85 ns
70 ns
85 ns
70 ns
85 ns
70 ns
85 ns
400-mil 32-pin plastic TSOP II reverse (TTP-32DR)
400-mil 32-pin plastic TSOP II (TTP-32D)
Package
525-mil 32-pin plastic SOP (FP-32D)
2
HM62V8512B Series
Pin Arrangement
HM62V8512BLFP Series
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
(Top view)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
(Top view)
HM62V8512BLRR Series
V
CC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
(Top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
HM62V8512BLTT Series
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
Pin Description
Pin name
A0 to A18
I/O0 to I/O7
CS
OE
WE
V
CC
V
SS
Function
Address input
Data input/output
Chip select
Output enable
Write enable
Power supply
Ground
3
HM62V8512B Series
Block Diagram
A18
A16
A1
A0
A2
A12
A14
A3
A7
A6
Row
Decoder
•
•
•
•
•
Memory Matrix
1,024
×
4,096
V
CC
V
SS
I/O0
Input
Data
Control
I/O7
•
•
Column I/O
Column Decoder
•
•
A13 A17A15 A8 A9 A11A10 A4 A5
•
•
CS
WE
OE
Timing Pulse Generator
Read/Write Control
4
HM62V8512B Series
Function Table
WE
×
H
H
L
L
CS
H
L
L
L
L
OE
×
H
L
H
L
Mode
Not selected
Output disable
Read
Write
Write
V
CC
current
I
SB
, I
SB1
I
CC
I
CC
I
CC
I
CC
Dout pin
High-Z
High-Z
Dout
Din
Din
Ref. cycle
—
—
Read cycle
Write cycle (1)
Write cycle (2)
Note:
×:
H or L
Absolute Maximum Ratings
Parameter
Power supply voltage
Voltage on any pin relative to V
SS
Power dissipation
Operating temperature
Storage temperature
Storage temperature under bias
Symbol
V
CC
V
T
P
T
Topr
Tstg
Tbias
Value
–0.5 to +4.6
–0.5*
1
to V
CC
+ 0.5*
2
1.0
–20 to +70
–55 to +125
–20 to +85
Unit
V
V
W
°C
°C
°C
Notes: 1. –3.0 V for pulse half-width
≤
30 ns
2. Maximum voltage is 4.6 V
Recommended DC Operating Conditions
(Ta = –20 to +70°C)
Parameter
Supply voltage
Symbol
V
CC
V
SS
Input high voltage
Input low voltage
Note:
V
IH
V
IL
Min
2.7
0
2.0
–0.3*
1
Typ
3.0
0
—
—
Max
3.6
0
V
CC
+ 0.3
0.8
Unit
V
V
V
V
1. –3.0 V for pulse half-width
≤
30 ns
5
微控制器 MCU
