HM62V8512CTS Series
4 M SRAM (512-kword
×
8-bit)
ADE-203-1258 (Z)
Preliminary
Rev. 0.0
Mar. 15, 2001
Description
The Hitachi HM62V8512CTS Series is a 4-Mbit static RAM organized 512-kword
×
8-bit. HM62V8512CTS
Series has realized higher density, higher performance and low power consumption by employing CMOS
process technology (6-transistor memory cell). It offers low power standby power dissipation; therefore, it is
suitable for battery backup system. It is packaged in TSOP I is available for high density surface mounting.
Features
•
Single 3.0 V supply: 2.7 V to 3.6 V
•
Access time: 55/70 ns (max)
•
Power dissipation
Active: 6.0 mW/MHz (typ)
Standby: 2.4 µW (typ)
•
Completely static memory. No clock or timing strobe required
•
Equal access and cycle times
•
Common data input and output: Three state output
•
Directly LV-TTL compatible: All inputs
•
Battery backup operation
Preliminary: The specification of this device are subject to change without notice. Please contact your
nearest Hitachi’s Sales Dept. regarding specification.
HM62V8512CTS Series
Ordering Information
Type No.
HM62V8512CLTS-5
HM62V8512CLTS-7
HM62V8512CLTS-5SL
HM62V8512CLTS-7SL
Access time
55 ns
70 ns
55 ns
70 ns
Package
8
×
13.4 mm 32-pin plastic TSOPI (TFP-32DC)
2
HM62V8512CTS Series
Pin Arrangement
32-pin TSOP (Normal Type TSOP)
A11
A9
A8
A13
WE
A17
A15
V
CC
A18
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
V
SS
I/O2
I/O1
I/O0
A0
A1
A2
A3
(Top view)
Pin Description
Pin name
A0 to A18
I/O0 to I/O7
CS
OE
WE
V
CC
V
SS
NC
Function
Address input
Data input/output
Chip select
Output enable
Write enable
Power supply
Ground
No connection
3
HM62V8512CTS Series
Block Diagram
LSB
V
CC
V
SS
•
•
•
•
•
MSB
A11
A9
A8
A15
A18
A10
A13
A17
A16
A14
A12
Row
Decoder
Memory Matrix
2,048
×
2,048
I/O0
Input
Data
Control
I/O7
•
•
Column I/O
Column Decoder
•
•
LSB A3 A2A1A0 A4 A5 A6 A7 MSB
•
•
CS
WE
OE
Timing Pulse Generator
Read/Write Control
4
HM62V8512CTS Series
Function Table
WE
×
H
H
L
L
CS
H
L
L
L
L
OE
×
H
L
H
L
Mode
Not selected
Output disable
Read
Write
Write
V
CC
current
I
SB
, I
SB1
I
CC
I
CC
I
CC
I
CC
Dout pin
High-Z
High-Z
Dout
Din
Din
Ref. cycle
—
—
Read cycle
Write cycle (1)
Write cycle (2)
Note:
×:
H or L
Absolute Maximum Ratings
Parameter
Power supply voltage
Voltage on any pin relative to V
SS
Power dissipation
Operating temperature
Storage temperature
Storage temperature under bias
Symbol
V
CC
V
T
P
T
Topr
Tstg
Tbias
Value
–0.5 to +4.6
–0.5*
1
to V
CC
+ 0.5*
2
1.0
–20 to +70
–55 to +125
–20 to +85
Unit
V
V
W
°C
°C
°C
Notes: 1. V
T
min: –3.0 V for pulse half-width
≤
30 ns.
2. Maximum voltage is 4.6 V.
Recommended DC Operating Conditions
(Ta = –20 to +70°C)
Parameter
Supply voltage
Symbol
V
CC
V
SS
Input high voltage
Input low voltage
Note:
V
IH
V
IL
Min
2.7
0
2.0
–0.3*
1
Typ
3.0
0
—
—
Max
3.6
0
V
CC
+ 0.3
0.8
Unit
V
V
V
V
1. V
IL
min: –3.0 V for pulse half-width
≤
30 ns.
5
