HANBit
HMN1288J
Non-Volatile SRAM MODULE 1Mbit (128K x 8-Bit),34Pin-JLCC, 5V
Part No. HMN1288J
GENERAL DESCRIPTION
The HMN1288J Nonvolatile SRAM is a 1,048,576-bit static RAM organized as 131,072 bytes by 8 bits.
The HMN1288J has a self-contained lithium energy source provide reliable non-volatility coupled with the unlimited write
cycles of standard SRAM and integral control circuitry which constantly monitors the single 5V supply for an out-of-
tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on to sustain the
memory until after Vcc returns valid and write protection is unconditionally enabled to prevent garbled data. In addition the
SRAM is unconditionally write-protected to prevent an inadvertent write operation. At this time the integral energy source is
switched on to sustain the memory until after V
CC
returns valid.
The HMN1288J uses extremely low standby current CMOS SRAM’s, coupled with small lithium coin cells to provide non-
volatility without long write-cycle times and the write-cycle limitations associated with EEPROM.
FEATURES
w
Access time : 55, 70 ns
w
High-density design : 4Mbit Design
w
Battery internally isolated until power is applied
w
Industry-standard 34-pin 128K x 8 pinout
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Unlimited write cycles
w
Data retention in the absence of V
CC
w
10-years minimum data retention in absence of power
w
Automatic write-protection during power-up/power-down
cycles
w
Data is automatically protected during power loss
w
Conventional SRAM operation; unlimited write cycles
/NBW
A(15)
A(16)
/RST
VCC
/WE
/OE
/CE
D(7)
D(6)
D(5)
D(4)
D(3)
D(2)
D(1)
D(0)
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
PIN ASSIGNMENT
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
NC
NC
A(14)
A(13)
A(12)
A(11)
A(10)
A(9)
A(8)
A(7)
A(6)
A(5)
A(4)
A(3)
A(2)
A(1)
A(0)
JLCC
TOP VIEW
OPTIONS
w
Timing
55 ns
70 ns
MARKING
-55
-70
URL: www.hbe.co.kr
Rev.0.0 (FEBRUARY/ 2002)
1
HANBit Electronics Co.,Ltd.
HANBit
HMN1288J
FUNCTIONAL DESCRIPTION
The HMN1288J executes a read cycle whenever /WE is inactive(high) and /CE is active(low). The address specified by
the address inputs(A
0
-A
16
) defines which of the 131,072 bytes of data is accessed. Valid data will be available to the eight
data output drivers within t
ACC
(access time) after the last address input signal is stable.
When power is valid, the HMN1288J operates as a standard CMOS SRAM. During power-down and power-up cycles, the
HMN1288J acts as a nonvolatile memory, automatically protecting and preserving the memory contents.
The HMN1288J is in the write mode whenever the /WE and /CE signals are in the active (low) state after address inputs
are stable. The later occurring falling edge of /CE or /WE will determine the start of the write cycle. The write cycle is
terminated by the earlier rising edge of /CE or /WE. All address inputs must be kept valid throughout the write cycle. /WE
must return to the high state for a minimum recovery time (t
WR
) before another cycle can be initiated. The /OE control
signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output bus been enabled
(/CE and /OE active) then /WE will disable the outputs in t
ODW
from its falling edge.
The HMN1288J provides full functional capability for Vcc greater than 4.75 V and write protects by 4.5 V nominal. Power-
down/power-up control circuitry constantly monitors the Vcc supply for a power-fail-detect threshold V
PFD
. When V
CC
falls
below the V
PFD
threshold, the SRAM automatically write-protects the data. All inputs to the RAM become
“don’t
care” and
all outputs are high impedance. As Vcc falls below approximately 2.7 V, the power switching circuit connects the lithium
energy soure to RAM to retain data. During power-up, when Vcc rises above approximately 2.7 volts, the power switching
circuit connects external Vcc to the RAM and disconnects the lithium energy source. Normal RAM operation can resume
after Vcc exceeds 4.75 volts.
BLOCK DIAGRAM
PIN DESCRIPTION
/OE
/WE
/CE1
A(0:16)
A
0
-A
16
: Address Input
DQ(0:7)
/CE : Chip Enable
V
SS
: Ground
DQ
0
-DQ
7
: Data In / Data Out
/WE : Write Enable
Vout
Vcc
/CE2
/CE
/RESET
/CE_con
Vcc
/OE : Output Enable
V
CC
: Power (+5V)
NC : No Connection
URL: www.hbe.co.kr
Rev.0.0 (FEBRUARY/ 2002)
2
HANBit Electronics Co.,Ltd.
HANBit
HMN1288J
TRUTH TABLE
MODE
Not selected
Output disable
Read
Write
/OE
X
H
L
X
/CE
H
L
L
L
/WE
X
H
H
L
I/O OPERATION
High Z
High Z
D
OUT
D
IN
POWER
Standby
Active
Active
Active
ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC voltage applied on V
CC
relative to V
SS
DC Voltage applied on any pin excluding V
CC
relative
to V
SS
Operating temperature
Storage temperature
Soldering temperature
SYMBOL
V
CC
V
T
T
OPR
T
STG
T
SOLDER
RATING
-0.3V to 7.0
-0.3V to Vcc+0.3
0 to 70°C
-55°C to 125°C
260°C
For 10 second
V
T
≤
V
CC
+0.3
CONDITIONS
NOTE:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded.
Functional operation should be restricted to the Recommended DC Operating Conditions detailed in this data sheet.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
( T
A
= T
OPR
)
PARAMETER
Supply Voltage
Ground
Input high voltage
Input low voltage
SYMBOL
V
CC
V
SS
V
IH
V
IL
MIN
4.5V
0
2.0
-0.3
TYPICAL
-
0
-
-
MAX
5.5V
0
V
CC+
0.3
0.8V
NOTE:
Typical values indicate operation at T
A
= 25℃
CAPACITANCE
(T
A
=25℃ , f=1MHz, V
CC
=5V)
DESCRIPTION
Input Capacitance
Input/Output Capacitance
CONDITIONS
Input voltage = 0V
Output voltage = 0V
SYMBOL
C
IN
C
I/O
MAX
8
10
MIN
-
-
UNIT
pF
pF
URL: www.hbe.co.kr
Rev.0.0 (FEBRUARY/ 2002)
3
HANBit Electronics Co.,Ltd.
HANBit
HMN1288J
DC ELECTRICAL CHARACTERISTICS
(T
A
= T
OPR
, V
CCmin
£
V
CC
≤
V
CCmax
)
PARAMETER
Input Leakage Current
Output Leakage Current
Output high voltage
Output low voltage
V
CC
Trip Point (TOL=GND)
Standby supply current
Standby supply current
Operating
current
V
CC
/V
BAT
Switch Point
NOTE:
Typical values indicate operation at T
A
= 25℃ .
Power
supply
/CE=2.2v
/CE≥ V
CC
-0.3V,
/CE=V
IL
, I
I/O
=0㎃ ,
V
IN
= V
IL
or V
IH,
Read
CONDITIONS
V
IN
=V
SS
to V
CC
/CE=V
IH
or /OE=V
IH
or /WE=V
IL
I
OH
=-1.0mA
I
OL
= 2.0mA
SYMBOL
I
LI
I
LO
V
OH
V
OL
V
CCTP
I
SB
I
SB1
I
CC
V
SW
MIN
-
-
2.4
-
4.5
-
-
-
2.6
TYP.
-
-
-
-
4.62
-
-
-
2.7
MAX
±
2.0
±
2.0
-
0.4
4.75
3
150
12
2.8
UNIT
mA
mA
V
V
V
mA
mA
mA
V
CHARACTERISTICS
(Test Conditions)
PARAMETER
Input pulse levels
VALUE
0.8 to 2.4V
5 ns
1.5V ( unless otherwise specified)
See Figures
CL1)
Input rise and fall times
Input and output timing reference
levels
1)
Output load (CL =50pF+1TTL)
1)
(CL =100pF+1TTL)
Including scope and jig capacitance
READ CYCLE
(T
A
= T
OPR
, V
CCmin
£
V
CC
≤
V
CCmax
)
PARAMETER
Read Cycle Time
Address Access Time
Chip enable access time
Output enable to Output valid
Chip enable to output in low Z
Output enable to output in low Z
Chip disable to output in high Z
Output disable to output high Z
Output hold from address change
SYMBOL
t
RC
t
ACC
t
ACE
t
OE
t
CLZ
t
OLZ
t
CHZ
t
OHZ
t
OH
Output load A
Output load A
Output load A
Output load B
Output load B
Output load B
Output load B
Output load A
CONDITIONS
-55
MIN
MAX
MIN
-70
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
55
-
-
10
5
0
0
10
-
55
55
25
-
-
20
20
-
70
-
-
-
10
5
0
0
10
-
70
70
35
-
-
25
25
-
URL: www.hbe.co.kr
Rev.0.0 (FEBRUARY/ 2002)
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HANBit Electronics Co.,Ltd.
HANBit
WRITE CYCLE
(T
A
= T
OPR
, V
ccmin
£
V
cc
≤
V
ccmax
)
PARAMETER
Write Cycle Time
Chip enable to end of write
Address setup time
Address valid to end of write
Write pulse width
Write recovery time (write cycle 1)
Write recovery time (write cycle 2)
Data valid to end of write
Data hold time (write cycle 1)
Data hold time (write cycle 2)
Write enabled to output in high Z
Output active from end of write
SYMBOL
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR1
t
WR2
t
DW
t
DH1
t
DH2
t
WZ
t
OW
Note 4
Note 4
Note 5
Note 5
Note 1
Note 2
Note 1
Note 1
Note 3
Note 3
CONDITIONS
-70
MIN
MAX
MIN
-85
HMN1288J
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
55
45
0
45
40
5
15
20
0
0
0
5
-
-
-
-
-
-
-
-
-
-
20
-
70
60
0
60
50
5
15
25
0
0
0
5
-
-
-
-
-
-
-
-
-
-
25
-
NOTE:
1. A write ends at the earlier transition of /CE going high and /WE going high.
2. A write occurs during the overlap of allow /CE and a low /WE. A write begins at the later transition of /CE
going low and /WE going low.
3. Either t
WR1
or t
WR2
must be met.
4. Either t
DH1
or t
DH2
must be met.
5. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain in high-
impedance state.
TIMING WAVEFORM
- READ CYCLE NO.1 (Address Access)*
1,2
t
RC
Address
t
ACC
t
OH
D
OUT
Previous Data Valid
Data Valid
- READ CYCLE NO.2 (/CE Access)
*1,3,4
/CE
t
ACE
t
CLZ
D
OUT
URL: www.hbe.co.kr
Rev.0.0 (FEBRUARY/ 2002)
t
RC
t
CHZ
High-Z
5
High-Z
HANBit Electronics Co.,Ltd.
