240pin Fully Buffered DDR2 SDRAM DIMMs based on 512 Mb F-ver.
This Hynix’s Fully Buffered DIMM is a high-bandwidth & large capacity channel solution that has a narrow
host interface. Hynix’s FB-DIMM features novel architecture including the Advanced Memory Buffer that
isolates the DDR2 SDRAMs from the channel. This single component located in the front side center of
each DIMM, acts as a repeater and buffer for all signals and commands which are exchanged between the
host controller and the DDR2 SDRAMs including data in and output. The AMB communicates with the host
controller and adjacent DIMMs on a system board using an industry standard Differential Point to Point
Link Interface at 1.5V power.
The AMB also allows buffering of memory traffic to support large memory capacities. All memory control
for the DDR2 SDRAM devices resides in the host, including memory request initiation, timing, refresh,
scrubbing, sparing, configuration access and power management. The AMB interface is responsible for
handling channel and memory requests to and from the local FBDIMM and for forwarding request to other
FBDIMMs on the memory channel.
FEATURES
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240 pin Fully Buffered ECC dual In-Line DDR2 SDRAM Module
JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply
All inputs and outputs are compatible with SSTL_1.8 interface
Built with 512Mb DDR2 SDRAMs in 60ball FBGA
Host interface and AMB component industry standard compliant
MBIST & IBIST test functions
4 Bank architecture
OCD (Off-Chip Driver Impedance Adjustment)
ODT (On-Die Termination)
Fully differential clock operations (CK & CK)
Programmable Burst Length 4 / 8 with both sequential and interleave mode
Auto refresh and self refresh supported
8192 refresh cycles / 64ms
Serial presence detect with EEPROM
133.35 x 30.35 mm form factor
RoHS compliant
Full Module Heat Spreader
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev 1.2 / Feb. 2009
1
1
240pin Fully Buffered DDR2 SDRAM DIMMs
ORDERING INFORMATION
# of
# of
DRAMs ranks
AMB
Vendor Version
Intel
IDT
Intel
IDT
Intel
IDT
D1
C1
D1
C1
D1
C1
Full
Module
30.35mm
H. S
type
Part Name
HMP564F7FFP8C-C4/Y5N3
HMP564F7FFP8C-C4/Y5/S5/S6D3
HMP512F7FFP8C-C4/Y5N3
HMP512F7FFP8C-C4/Y5/S5/S6D3
HMP525F7FFP4C-C4/Y5N3
HMP525F7FFP4C-C4/Y5D3
Density
Org.
Height
512MB
64Mx72
9
1
1GB
128Mx72
18
2
2GB
256Mx72
36
2
Note:
*: The 16th and 17th digits stand for AMB vendor and revision.
SPEED GRADE & KEY PARAMETERS
Speed Grade
DDR2 DRAM Speed Grade
FB-DIMM Speed Grade
FB-DIMM Peak Channel Throughput
FB-DIMM Link Transfer Rate
C4
DDR2 533 4-4-4
PC2 4200
6.4
3.2
Y5
DDR2 667 5-5-5
PC2 5300
8.0
4.0
S5/6
DDR2 800 5-5-5 / 6-6-6
PC2 6400
9.6
4.8
GByte/S
GT/s
Unit
ADDRESS TABLE
Density
512MB
1GB
2GB
Org.
64M x 72
128M x 72
256M x 72
Ranks
1
2
2
SDRAMs
64Mbx8
64Mbx8
128Mbx4
# of
DRAMs
9
18
36
# of row/bank/column Address
14(A0~A13)/2(BA0~BA1)/10(A0~A9)
14(A0~A13)/2(BA0~BA1)/10(A0~A9)
14(A0~A13)/2(BA0~BA1) 11(A0~A9,A11)
Refresh
Method
8K / 64ms
8K / 64ms
8K / 64ms
Rev 1.2 / Feb. 2009
2
1
240pin Fully Buffered DDR2 SDRAM DIMMs
Input/Output Functional Description
Pin Name
SCK
SCK
PN[13:0]
PN[13:0]
PS[9:0]
PS[9:0]
SN[13:0]
SN[13:0]
SS[9:0]
SS[9:0]
SCL
SDA
SA[2:0]
VID[1:0]
RESET
RFU
VCC
VDD
VTT
VDDSPD
VSS
type
Input
Input
Output
Output
Input
Input
Output
Output
Input
Input
Input
Input / Output
Input
Input
Input
-
Supply
Supply
Supply
Supply
Supply
Polarity
Positive
Negative
Positive
Negative
Positive
Negative
Positive
Negative
Positive
Negative
-
-
-
-
Active Low
-
+1.5V
+1.8V
+0.9V
+3.3V
System clock input
System clock input
Primary Northbound Data
Primary Northbound Data
Primary Southbound Data
Primary Southbound Data
Secondary Northbound Data
Secondary Northbound Data
Secondary Southbound Data
Secondary Southbound Data
Serial Presence Detect (SPD) Clock Input
SPD Data Input / Output
SPD Address inputs, also used to select the DIMM number in the AMB
Voltage ID:
These pins must be unconnected for DDR2-based Fully buffered DIMMs
AMB reset signal
Reserved for Future Use
AMB Core Power and AMB channel Interface Power(1.5volt)
DRAM Power and AMB DRAM I/O Power
DRAM Address/Command/Clock Termination Power(VDD/2)
SPD Power
Ground
The DNU/M_Test pin provides an external connection on R/Cs A-D for
testing the margin of Vref which is produced by a voltage divider on the
module. It is not intended to be used in normal system operation and
must not be connected(DNU) in a system. This test pin may have other
features on future card designs and if it does, will be included in this
specification at that time.
Total
Function Description
Count
1
1
14
14
10
10
14
14
10
10
1
1
3
2
1
16
8
24
4
1
80
1
DNU/
M_Test
- / Analog
- / 0.9V
240
Rev 1.2 / Feb. 2009
3
1
240pin Fully Buffered DDR2 SDRAM DIMMs
PIN ASSIGNMENT
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Name
VDD
VDD
VDD
VSS
VDD
VDD
VDD
VSS
VCC
VCC
VSS
VTT
VCC
VSS
VTT
VID1
RESET
VSS
RFU**
RFU**
VSS
PN0
PN0
VSS
PN1
PN1
VSS
PN2
PN2
VSS
PN3
PN3
VSS
PN4
PN4
VSS
PN5
PN5
VSS
PN13
69
70
71
72
73
74
75
76
77
78
79
80
Pin
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Key
VSS
PS0
PS0
VSS
PS1
PS1
VSS
PS2
PS2
VSS
PS3
PS3
Name
PN13
VSS
VSS
RFU*
RFU*
VSS
VSS
PN12
PN12
VSS
PN6
PN6
VSS
PN7
PN7
VSS
PN8
PN8
VSS
PN9
PN9
VSS
PN10
PN10
VSS
PN11
PN11
VSS
Pin
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Name
VSS
PS4
PS4
VSS
VSS
RFU*
RFU*
VSS
VSS
PS9
PS9
VSS
PS5
PS5
VSS
PS6
PS6
VSS
PS7
PS7
VSS
PS8
PS8
VSS
RFU**
RFU**
VSS
VDD
VDD
VSS
VDD
VDD
VDD
VSS
VDD
VDD
VTT
SA2
SDA
SCL
Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
Name
VDD
VDD
VDD
VSS
VDD
VDD
VDD
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VTT
VID0
DNU/M_Test
VSS
RFU**
RFU**
VSS
SN0
SN0
VSS
SN1
SN1
VSS
SN2
SN2
VSS
SN3
SN3
VSS
SN4
SN4
VSS
SN5
SN5
VSS
SN13
189
190
191
192
193
194
195
196
197
198
199
200
NC= No Connect, RFU= Reserved for Future Use.
Pin
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
Key
VSS
SS0
SS0
VSS
SS1
SS1
VSS
SS2
SS2
VSS
SS3
SS3
Name
SN13
VSS
VSS
RFU*
RFU*
VSS
VSS
SN12
SN12
VSS
SN6
SN6
VSS
SN7
SN7
VSS
SN8
SN8
VSS
SN9
SN9
VSS
SN10
SN10
VSS
SN11
SN11
VSS
Pin
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Name
VSS
SS4
SS4
VSS
VSS
RFU*
RFU*
VSS
VSS
SS9
SS9
VSS
SS5
SS5
VSS
SS6
SS6
VSS
SS7
SS7
VSS
SS8
SS8
VSS
RFU*
RFU*
VSS
SCK
SCK
VSS
VDD
VDD
VDD
VSS
VDD
VDD
VTT
VDDSPD
SA0
SA1
Note:
*: These pin positions are reserved for forwarded clocks to be used in future module implementations
**: These pin positions are reserved for future architecture flexibility
1) The following signals are CRC bits and thus appear out of the normal sequence:
PN12/ PN12, SN12 / SN12, PN13 / PN13, SN13 / SN13,PS9 / PS9, SS9 / SS9
Rev 1.2 / Feb. 2009
4
1
240pin Fully Buffered DDR2 SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
512MB(64Mbx72) ECC FB-DIMM
/S0
DQS0
/DQS0
DQS9
DM
NU /CS
RDQS /RDQS
I/O 0
I/O 1
I/O 2
I/O
I/O
I/O
I/O
I/O
3
4
5
6
7
DQS
/DQS
DQS4
/DQS4
DQS13
DM
NU /CS
RDQS /RDQS
I/O 0
I/O 1
I/O 2
I/O
I/O
I/O
I/O
I/O
3
4
5
6
7
DQS
/DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
/DQS1
DQS10
D0
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
/DQS5
DQS14
D4
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
/DQS2
DQS11
DM
NU /CS
RDQS /RDQS
I/O 0
I/O 1
I/O 2
I/O
I/O
I/O
I/O
I/O
3
4
5
6
7
DQS
/DQS
D1
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS6
/DQS6
DQS15
DM
NU /CS
RDQS /RDQS
I/O 0
I/O 1
I/O 2
I/O
I/O
I/O
I/O
I/O
3
4
5
6
7
DQS
/DQS
D5
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
/DQS3
DQS12
DM
NU /CS
RDQS /RDQS
I/O 0
I/O 1
I/O 2
I/O
I/O
I/O
I/O
I/O
3
4
5
6
7
DQS
/DQS
D2
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
/DQS7
DQS16
DM
NU /CS
RDQS /RDQS
I/O 0
I/O 1
I/O 2
I/O
I/O
I/O
I/O
I/O
3
4
5
6
7
DQS
/DQS
D6
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
NU /CS
RDQS /RDQS
I/O 0
I/O 1
I/O 2
I/O
I/O
I/O
I/O
I/O
3
4
5
6
7
DQS
/DQS
D3
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
V
TT
DQS8
/DQS8
DQS17
DM
NU /CS
RDQS /RDQS
I/O 0
I/O 1
I/O 2
I/O
I/O
I/O
I/O
I/O
3
4
5
6
7
DQS
/DQS
D7
All address/command/control/clock
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM
NU /CS
RDQS /RDQS
I/O 0
I/O 1
I/O 2
I/O
I/O
I/O
I/O
I/O
3
4
5
6
7
DQS
/DQS
D8
Serial PD
SCL
SCL
WP
A0
U0
A1
SDA
A2
SA2
SDA
VTT
VCC
VDD SPD
VDD
VREF
VSS
Terminators
AMB
Serial PD,AMB
DO-D8, AMB
DO-D8
DO-D8,SPD, AMB
PN0-PN13
/PN0-/PN13
PS0-PS9
/PS0-/PS9
DQ0-DQ63
CB0-CB7
DQS0-DQS17
/DQS0-/DQS8
SCL
SDA
SA0-SA2
/RESET
SCK/ /SCK
A
M
B
SN0-SN13
/SN0-/SN13
SS0-SS9
/SS0-/SS9
/S0-/CS(all SDRAMs)
CKE0 -> CKE
ODT -> ODT
BA0-BA2
A0-A15
/RAS
/CAS
/WE
CK/ /CK
SA0 SA1
Notes :
1. DQ-to-I/O wiring may be changed within a byte.
2. There are two physical copies of each address/command/control/clock.
Rev 1.2 / Feb. 2009
5
