HMXDAC01
Radiation Hardened 12-Bit,
Monolithic D/A Converter
Features
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Monolithic 12-Bit D/A Converter
Rad Hard: >300k Rad(Si) Total Dose
Single +5 V Analog Supply
5V or 3.3V Digital and I/O Supply
Offset Error: < ±0.2% FSR
Offset Temperature Coefficient:
< ±50PPM of FSR/°C
Gain Error: < ±3% FSR
Gain Temperature Coefficient: < ±150
PPM of FSR/°C
Integral Nonlinearity Error: < ±3 LSB
Differential Nonlinearity Error: < ±1 LSB
Settling Time to 1LSB: < 1.4µs
Full Scale Range: 0mA to 5mA
(0V to 2V into 400Ω)
Power Supply Rejection Ratio PSRR:
< ±0.35 %FSR/V
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Mixed Signal Rad Hard Process
The HMXDAC01 is fabricated on space
qualified SOI CMOS process. High-
speed precision analog circuits are
now combined with high-density logic
circuits that can reliably withstand the
harshest environments.
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Low Power
The HMXDAC01 at 85 mW maximum
consumes a fraction of the power
of presently available monolithic
solutions.
The HMXDAC01 is a radiation hardened
monolithic, single supply, 12-bit, digital-
to-analog converter. The HMXDAC01 is a
12 bit differential current steering DAC. It
is a 6 x 2 x 4 doubly segmented architec-
ture with the six MSBs linearly decoded
and the four LSBs binary decoded. The
intermediate two bits are linearly decoded.
The six MSBs employ a two dimensional
hierarchical symmetrical switching
sequence to compensate and average
two dimensional matching errors.
The HMXDAC01 is fabricated on
radiation hardened SOI-IV Silicon On
Insulator (SOI) CMOS process with very
low power consumption.
The input of the HMXDAC01 allows for
easy interfacing to space and military
imaging, sensor, and communications
systems.
A single clock input is used to control
all internal conversion cycles.
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Dual Power Supply Capability
The HMXDAC01 uses a single +5
V power supply simplifying system
power supply design. It also features
a separate digital driven supply
line to accommodate 3.3 V and
5 V logic families.
Block
Diagram
VDDA VSSA VDD VSS
RFB
Rset
D/A Converter and
Output Drivers
D0 – D11
START
VREF IN
Buffer
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Space Qualified Package
The HMXDAC01 is packaged in
a 28 lead quad ceramic flat pack.
IOUT
IOUTN
RDAC
RDAC
Pinout
Diagram
23
VDDA
22
VSSA
DB10
26
DB11
28
DB9
25
VSS
VDD
Pin Description
Pin
1
2
3
4
21
19
IOUT
IOUTN
NC
RFB
NC
VREF_IN
Pin Name
DB8
DB7
DB6
START
DB5
DB4
DB3
DB2
DB1
DB0
VSS
VDD
VDDA
VSSA
VREF_IN
NC
RFB
NC
IOUTN
NC
IOUT
VSSA
VDDA
VDD
VSS
DB11
DB10
DB9
Description
Data Bit 8
Data Bit 7
Data Bit 6
Clock Input
Data Bit 5
Data Bit 4
Data Bit 3
Data Bit 2
Data Bit 1
Data Bit 0 (LSB)
Digital Ground
Digital Supply Voltage
Analog Supply Voltage
Analog Ground
Bias Control
No Connect
Feedback Resistor Input, (Rset to GND)
No Connect
Remainder Output Current, (RDAC to GND)
No Connect
Output Current, (RDAC to GND)
Analog Ground
Analog Supply Voltage
Digital Supply Voltage
Digital Ground
Data Bit 11 (MSB)
Data Bit 10
Data Bit 9
24
27
DB8
DB7
DB6
START
DB5
DB4
DB3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
20
NC
HMXDAC01
18
17
16
15
DB2
VDDA
DB1
DB0
VSS
VDD
VSSA
Signal Definition
Name
DB0-DB11
START
VREF_IN
IOUT
Description
The digital data input pins control the value of the output current. DB11 is the most
significant bit (MSB) and DB0 is the Least Significant Bit (LSB).
This is the clock signal which initiates a conversion. The positive going edge latches in
the data present on the DB0-DB11 pins.
This is the reference voltage input pin. A 2V reference voltage is required by the circuit.
This is the output current. This will be in the range of 0mA to 5mA based on the 12 bit input
code. This pin is normally connected through a RDAC resistor to ground. The value of RDAC
is suggested to be 400Ω. This value of RDAC will give an output voltage range of 0V to 2V.
IOUTN
RFB
This is the remainder of the full scale current specified by the 12 bit input code. This pin is
normally connected through a RDAC resistor to ground.
This is the feedback resistor pin. A feedback resistor Rset is required to be connected
from GND to the RFB pin. The typical value for Rset is 25.59 +/- .01% Kohms.
Absolute Maximum Ratings (1)(2)
Parameter
Analog Supply Voltage
Digital Supply Voltage
Power Dissipation
Vref Input Voltage 3/
Vref Input Current
Digital Input Voltage 3/
Digital Input Current
Thermal Resistance, Junction to Case
Junction Temperature
ESD HBM 1.5K ohms, 100pF
(Handling/Manufacturing)
Lead Temperature
(Soldering, 10 seconds)
(1) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
(2) VSSA=VSS = 0 volts
(3) Absolute maximum value not to exceed 6.5 V.
TLMAX
300
°C
DB0 – DB11, START
IDB0 – IDB11, ISTART
–
0 JC
TJ
Radiation Performance
Min
-0.5
-0.5
-0.5
-50
-0.5
-50
Symbol
VDDA
VDD
PD
VREF_IN
Limits
Max
6.5
6.5
150
Units
Volt
Volt
mW
Volt
mA
Volt
mA
°C /W
°C
V
VDDA+0.5
50
VDD+0.5
50
8.1
175
500
Total Ionizing Radiation Dose
The HMXDAC01 will meet all stated functional
and electrical specifications after the specified
total ionizing radiation dose. All electrical and
timing performance parameters will remain
within specifications, post rebound (based
on extrapolation), after an operational period
of 15 years. Total dose hardness is assured
by wafer level testing of process monitor
transistors using 10 KeV X-ray. Parameter
correlations have been made between 10
KeV X-rays applied at a dose rate of 5x10
5
rad(SiO
2
)/min at T= 25°C and gamma rays
(Cobalt 60 source) to ensure that wafer level
X-ray testing is consistent with standard
military radiation test environments.
Transient Pulse Ionizing Radiation
The HMXDAC01 will meet any functional
or electrical specification after exposure to
a radiation pulse up to the transient dose
rate survivability specification, when applied
under recommended operating conditions.
Note that the current conducted during
the pulse by the DAC inputs, outputs, and
power supply may significantly exceed the
normal operating levels. The application
design must accommodate these effects.
Neutron Radiation
The device will meet any functional or
timing specification after exposure to the
specified neutron fluence under recom-
mended operating or storage conditions.
Latchup and Snapback
The HMXDAC01 will not latch up due to any
of the above radiation exposure conditions
when applied under recommended
operating conditions. Fabrication with
the SIMOX substrate material provides
oxide isolation between adjacent PMOS
and NMOS transistors and eliminates
any potential SCR latchup structures.
Sufficient transistor body tie connections
to the p- and n-channel substrates
are made to ensure no source/drain
snapback occurs.
Recommended Operating Conditions (1)
Parameter
Clock Frequency
Analog Supply Voltage
Digital Supply Voltage
Bias Control
Case Operating Temperature
Feedback Resistor
IOUT Resistor
VDDA
VDD
VREF_IN
TC
Rset
RDAC
Symbol
Min
>0
4.75
3.135
Limits
Max
3
5.25
3.465
2.002
125
26
400.4
Units
MHz
V
V
V
°C
Kohms
ohms
1.998
-55
25
399.6
(1) All voltages are with respect to VSSA = VSS = 0.0 volts.
Functional Description
The HMXDAC01 is a 12 bit differential current steering DAC. It is a 6x2x4 doubly segmented
architecture with the six MSBs linearly decoded and the four LSBs binary decoded. The
intermediate two bits are linearly decoded.
The total output current available from the DAC is 5mA. Based on the digital input code,
a fraction of the 5mA is steered to the IOUT pin while the remaining portion of the 5mA is
steered to the IOUTN pin. In order to convert the current output into a voltage output, an
external resistor is required. A resistor, RDAC, needs to be connected from IOUT to ground
and from IOUTN to ground. A value of 400Ω for RDAC will give an output voltage range of
0V to 2V. The full scale current output is determined by Rset and Vref as described by the
following equations:
Iref = Vref/Rset
Iout (full scale) = 64*Iref => 5 mA
Radiation Hardness Ratings (1)(2)
Parameter
Total Dose (3)
Transient Dose Rate Upset
Dose Rate Survivability
Neutron Fluence
Limits
≥300
≥1x10
9
12
14
Units
krad(Si)
rad(Si)/s
rad(Si)/s
N/cm
2
Test Conditions
VDD= Maximum
PW = 20ns, 3µs X-ray, VDD = Minimum
PW = 20ns, 3µs X-ray, VDD = Maximum
1MeV equivalent energy, Unbiased
≥1
x10
≥1
x10
(1) Ambient temperature 25°C unless otherwise specified.
(2) Device will not latch up due to any of the specified radiation exposure conditions.
(3) Parts tested to 300krad without accelerated annealing.
Electrical Requirements (1)
VDDA=5.0 +/- 5%, VDD=3.3 +/- 5%, VSSA=VSS=0.0V, T
C
=-55°C to 125°C, Rset=25.6KΩ, VREF_IN=2.0V, RDAC=400Ω
(unless otherwise specified)
Parameter
Offset Error
Gain Error
DC ACCURACY
Integral Nonlinearity
Differential Nonlinearity
Offset Temperature Coefficient
Gain Temperature Coefficient
Settling Time for half scale code transition (±1 LSB)
Settling Time for 1/16th scale code transition (±1 LSB)
DAC Output Capacitance
High Level Input Voltage (minimum)
Low Level Input Voltage (maximum)
High Level Input Current
Low Level input Current
Analog Power Supply Current
Digital Power Supply Current
D.C. Differential
PSRR
(1)
(2)
(3)
(4)
Monotonicity guaranteed by DNL test.
Peak fit method is used on Offset Error, Gain Error, DNL and INL measurements.
PSRR = (gain error at 5.25V – gain error at 4.75V) / (5.25 V – 4.75 V).
This parameter is guaranteed by Design.
INL
DNL
OFFSET_TC
GAIN_TC
t
S1
t
S2
C
OUT
V
IH
V
IL
I
IH
I
IL
I
DDA
I
DDD
PSRR
(4)
VDD = 3.135V
VDD = 3.135V
VDD=3.465V, Vin = 3.465V
VDD=3.465V, Vin = 0.0V
bits = 1
V
IN
=V
DD
, V
DD
=3.465V, V
DDA
=5.25V
bits = 1
V
IN
=V
DD
, V
DD
=3.465V, V
DDA
=5.25V
VDDA= +4.75V to +5.25V
VDD=3.3 V 3/
-0.35
0.35
%FSR/V
-
6.25
mA
-
12.5
mA
see Note (2)
see Note (2)
-3.0
-0.99
-50
-150
-
-
-
2.31
-
-20
-20
3.0
0.99
50
150
2.5
1.4
15
-
.99
20
20
LSB
LSB
ppm of FSR/C
ppm of FSR/C
µS
µS
pF
V
V
µA
µA
Symbol
OFFSET
GAIN
Conditions
see Note (2)
see Note (2)
Min
-0.2
-3.0
Max
0.2
3.0
Unit
%FSR
%FSR
ESD (Electrostatic Discharge) Sensitive
The HMXDAC01 is rated as Class 1B ESD (500V). Proper ESD precautions should be taken to avoid degradation or damage to the device.
Timing Requirements
VDDA=5.0 +/- 5%, VDD=3.3 +/- 5%, VSSA=VSS=0.0V, T
C
=-55°C to 125°C, Rset=25.6KΩ,
VREF_IN=2.0V, RDAC=400Ω (unless otherwise specified)
Parameter
Clock Frequency
Analog Supply Voltage
Digital Supply Voltage
Bias Control
Case Operating Temperature
Feedback Resistor
IOUT Resistor
VDDA
VDD
VREF_IN
TC
Rset
RDAC
Timing Diagram
3.3V
Symbol
Min
>0
4.75
3.135
Limits
Start
Max
3
5.25
3.465
2.002
125
26
400.4
Units
MHz
V
V
V
°C
Kohms
ohms
0V
T
ds
Data
Input
t
DH
3.3V
1.998
-55
25
399.6
0V
(1) All voltages are with respect to VSSA = VSS = 0.0 volts.
Typical INL
4
3
2
1
0
-1
-2
-3
-4
0
1000
2000
Input Code
3000
4000
Qualification and Screening
The SOI CMOS technology is qualified by Honeywell after meeting
the criteria of the General Manufacturing Standards and is also
QML Qualified. This qualification is the culmination of years of
development, testing, documentation, and on-going process control.
The test flow includes screening units with the defined flow
(Class V and Q+ equivalent) and the appropriate periodic or lot
conformance testing (Groups B, C, D, and E). Both the process
and the products are subject to period or lot based Technology
Conformance Inspection (TCI) and Quality Conformance
Inspection (QCI) tests, respectively, as defined by Honeywell’s
Quality Management Plan.
Honeywell delivers products that are screened to two levels
including Engineering Models and Flight Units. EMs are
available with limited screening for prototype development
and evaluation testing.
Group A
Group B
Group C
Group D
Final Lot Acceptance Electrical Tests
Mechanical – Dimensions (1), Bond Strength, Solvents, Die Shear,
Solderability, Lead Integrity, Seal, Acceleration
Life Tests – 1000 hours at 125°C or equivalent
Package related mechanical tests – Shock, Vibration, Accel, Salt (1),
Seal, Lead Finish Adhesion, Lid Torque, Thermal Shock, Temp Cycle,
Moisture Resistance
Group E
Radiation Tests
Reliability
For many years Honeywell has been producing integrated circuits
that meet the stringent reliability requirements of space and
defense systems. Honeywell has delivered hundreds of thousands
of QML parts since first becoming QML qualified in 1990. Using
this proven approach Honeywell will assure the reliability of the
products manufactured with the SOI CMOS process technology.
This approach includes adhering to Honeywell’s General
Manufacturing Standards for:
• Designing in reliability by establishing electrical rules based on
wear out mechanism characterization performed on specially
designed test structures (electromigration, TDDB, hot carriers,
negative bias temperature instability, radiation)
• Utilizing a structured and controlled design process
• A statistically controlled wafer fabrication process with a
continuous defect reduction process
• Individual wafer lot acceptance through process monitor testing
(includes radiation testing)
• The use of characterized and qualified packages
• A thorough product testing program based on MIL-PRF-38535
and MIL-STD 883.
LSB
(1) Testing performed by package supplier.
