HN62W4416 Series
1048576-word
×
16-bit/2097152-word
×
8-bit CMOS Mask
Programmable ROM
ADE-203-469(Z)
Preliminary
Rev. 0.0
Nov. 20, 1995
Description
The HN62W4416 is a 16-Mbit CMOS mask-Programmable ROM organized either as 1048576 words by 16
bits or 2097152 words by 8 bits. Realizing low power consumption, this memory is allowed for battery
operation. And a high speed access of 150 ns (max) is the most suitable to the system using a high speed
micro-computer by 16 bits.
Feature
•
Low voltage operation Mask ROM
Single 3.3 V supply
•
High speed
Access time: 150 ns (max)
•
Low power
Active: 216 mW (max)
Standby: 108
µW
(max)
•
Byte-wide or word-wide data organization (Switched by BHE terminal)
•
Three-state data output for or-tying
•
Directly LVTTL compatible
All inputs and outputs
Ordering Information
Type No.
HN62W4416P-15
HN62W4416FB-15
HN62W4416TT-15
Access time
150 ns
150 ns
150 ns
Package
600 mil 42-pin plastic DIP (DP-42)
600 mil 44-pin plastic SOP (FP-44D)
400 mil 44-pin plastic TSOP II (TTP-44D)
Note: The specifications of this device are subject to change without notice. Please contact your nearest
Hitachi’s Sales Dept. regarding specifications.
HN62W4416 Series
Pin Arrangement
HN62W4416P Series
HN62W4416FB Series
HN62W4416TT Series
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BHE
V
SS
D15/A-1
D7
D14
D6
D13
D5
D12
D4
V
DD
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
V
SS
OE
D0
D8
D1
D9
D2
D10
D3
D11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
(Top View)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BHE
V
SS
D15/A-1
D7
D14
D6
D13
D5
D12
D4
V
DD
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
V
SS
OE
D0
D8
D1
D9
D2
D10
D3
D11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
(Top View)
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
Pin Description
Pin name
A-1, A0 to A19
D0 to D15
BHE
CE
OE
NC
V
DD
V
SS
Function
Address inputs
Data outputs
8/16 bit (byte/word) mode switch
Chip enable
Output enable
No connection
Power supply
Ground
2
HN62W4416 Series
Block Diagram
A19
A8
Address
Buffer
A7
Y Decoder
A0
Y Gates
X Decoder
Memory Array
(A-1)
*1
Hex/Byte
BHE
OE
3-state output
buffer
CE
D0
BHE = V
IH
: 16-bit (D15 to D0)
BHE = V
IL
: 8-bit (D7 to D0)
Note : 1. A-1 is least significant address.
When BHE is 'low', D14 to D8 goes the high impedance state, and D15 should be A-1.
D15/(D7)
Mode Selection
Pin
Data output
Mode
Standby
Output disable
Read (16-bit)
Read (8-bit)
Read (8-bit)
CE
H
L
L
L
L
OE
×
*1
H
L
L
L
BHE
×
×
H
L
L
D15/A-1 D0-D7
×
×
Dout
L
H
High-Z
*2
High-Z
D0 to D7
D0 to D7
D8 to D15
D8-D15
High-Z
High-Z
D8 to D15
High-Z
High-Z
Address input
LSB
—
—
A0
A-1
A-1
MSB
—
—
A19
A19
A19
Notes: 1.
×:
Don’t care.
2. High-Z: High impedance
3
HN62W4416 Series
Absolute Maximum Ratings
Parameter
Supply voltage
*1
All input and output voltage
*1
Operating temperature range
Storage temperature range
Temperature under bias
Note:
1. With respect to V
SS
.
Symbol
V
DD
Vin, Vout
Topr
Tstg
Tbias
Value
–0.3 to +5.5
–0.3 to V
DD
+ 0.3
0 to +70
–55 to +125
–20 to +85
Unit
V
V
°C
°C
°C
Recommended DC Operating Conditions
(Ta = 0 to + 70°C)
Parameter
Supply voltage
Symbol
V
DD
V
SS
Input voltage
V
IH
V
IL
Min
3.0
0
2.2
–0.3
Typ
3.3
0
—
—
Max
3.6
0
V
DD
+ 0.3
0.8
Unit
V
V
V
V
DC Characteristics
(V
DD
= 3.3 V
±
0.3 V, V
SS
= 0 V, Ta = 0 to + 70°C)
Parameter
Supply current
Active
Standby
Standby
Input leakage current
Output leakage current
Output voltage
Symbol
I
DD
I
SB1
I
SB2
|I
IL
|
|I
OL
|
V
OH
V
OL
Min
—
—
—
—
—
2.4
—
Max
60
30
3
10
10
—
0.4
Unit
mA
µA
mA
µA
µA
V
V
Test conditions
V
DD
= 3.6 V, I
DOUT
= 0 mA, t
RC
= 150 ns
V
DD
= 3.6 V,
CE
≥
V
DD
– 0.2 V
V
DD
= 3.6 V,
CE
≥
2.2 V
Vin = 0 to V
DD
CE
= 2.2 V, Vout = 0 to V
DD
I
OH
= –2.0 mA
I
OL
= 2.0 mA
Capacitance
(V
DD
= 3.3 V
±
0.3 V, V
SS
= 0 V, Ta = 25°C, Vin = 0 V, f = 1MHz)
Parameter
Input capacitance
*1
Output capacitance
*1
Note:
Symbol
Cin
Cout
Min
—
—
Max
10
15
Unit
pF
pF
1. This parameter is sampled and not 100% tested. D15/A-1 pin is output.
4
HN62W4416 Series
AC Characteristics
(V
DD
= 3.3 V
±
0.3 V, V
SS
= 0 V, Ta = 0 to + 70°C)
•
•
•
•
Output load: 1TTL + C
L
= 100 pF (including jig)
Input pulse level: 0.4 to 2.4 V
Input and output timing reference level: 1.4 V
Input rise and fall time: 5 ns
HN62W4416-15
Parameter
Read cycle time
Address access time
CE
access time
OE
access time
BHE access time
Output hold time from address change
Output hold time from
CE
Output hold time from
OE
Output hold time from BHE
CE
to output in high-Z
OE
to output in high-Z
BHE to output in high-Z
CE
to output in low-Z
OE
to output in low-Z
BHE to output in low-Z
Note:
Symbol
t
RC
t
AA
t
ACE
t
OE
t
BHE
t
DHA
t
DHC
t
DHO
t
DHB
t
CHZ
t
OHZ
t
BHZ
t
CLZ
t
OLZ
t
BLZ
Min
150
—
—
—
—
5
0
0
0
—
—
—
5
5
5
Max
—
150
150
50
150
—
—
—
—
50
50
30
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
Note
1. t
CHZ
, t
OHZ
and t
BHZ
are defined as the time at which the output achieves the open circuit conditions
and are not referred to output voltage levels.
5
