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HS0-5104ARH-Q

QUAD OP-AMP, 3000uV OFFSET-MAX, 8MHz BAND WIDTH, UUC14, DIE-14

器件类别:模拟混合信号IC    放大器电路   

厂商名称:Renesas(瑞萨电子)

厂商官网:https://www.renesas.com/

器件标准:  

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器件参数
参数名称
属性值
是否无铅
不含铅
是否Rohs认证
符合
厂商名称
Renesas(瑞萨电子)
零件包装代码
DIE
包装说明
DIE,
针数
14
Reach Compliance Code
compliant
ECCN代码
USML XV(E)
放大器类型
OPERATIONAL AMPLIFIER
最大平均偏置电流 (IIB)
0.3 µA
标称共模抑制比
80 dB
最大输入失调电压
3000 µV
JESD-30 代码
R-XUUC-N14
JESD-609代码
e4
负供电电压上限
-20 V
标称负供电电压 (Vsup)
-15 V
功能数量
4
端子数量
14
封装主体材料
UNSPECIFIED
封装代码
DIE
封装形状
RECTANGULAR
封装形式
UNCASED CHIP
峰值回流温度(摄氏度)
NOT SPECIFIED
认证状态
Not Qualified
筛选级别
MIL-PRF-38535 Class V
标称压摆率
2 V/us
供电电压上限
20 V
标称供电电压 (Vsup)
15 V
表面贴装
YES
技术
BIPOLAR
端子面层
Gold (Au)
端子形式
NO LEAD
端子位置
UPPER
处于峰值回流温度下的最长时间
NOT SPECIFIED
总剂量
100k Rad(Si) V
标称均一增益带宽
8000 kHz
文档预览
HS-5104ARH
Data Sheet
August 1999
File Number
3025.3
Radiation Hardened Low Noise Quad
Operational Amplifier
The HS-5104ARH is a radiation hardened, monolithic quad
operational amplifier that provides highly reliable
performance in harsh radiation environments. Its excellent
noise characteristics coupled with an unique array of
dynamic specifications make this amplifier well-suited for a
variety of satellite system applications. Dielectrically
isolated, bipolar processing makes this device immune to
Single Event Latch-Up.
The HS-5104ARH shows almost no change in offset voltage
after exposure to 100kRAD(Si) gamma radiation, with only a
minor increase in current. Complementing these specifications
is a post radiation open loop gain in excess of 40K.
This quad operational amplifier is available in an industry
standard pinout, allowing for immediate interchangeability
with most other quad operational amplifiers.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-95690. A “hot-link” is provided
on our homepage for downloading.
http://www.intersil.com/spacedefense/space.htm
Features
• Electrically Screened to SMD # 5962-95690
• QML Qualified per MIL-PRF-38535 Requirements
• Radiation Environment
- Gamma Dose (γ) . . . . . . . . . . . . . . . . . 1 x 10
5
RAD(Si)
• Low Noise
- At 1kHz . . . . . . . . . . . . . . . . . . . . . . . . 4.3nV/√Hz (Typ)
- At 1kHz . . . . . . . . . . . . . . . . . . . . . . . . 0.6pA/√Hz (Typ)
• Low Offset Voltage . . . . . . . . . . . . . . . . . . . . 3.0mV (Max)
• High Slew Rate . . . . . . . . . . . . . . . . . . . . . . 2.0V/µs (Typ)
• Gain Bandwidth Product . . . . . . . . . . . . . . . 8.0MHz (Typ)
Applications
• High Q, Active Filters
• Voltage Regulators
• Integrators
• Signal Generators
• Voltage References
• Space Environments
Ordering Information
ORDERING NUMBER
5962R9569001V9A
5962R9569001VCC
5962R9569001VXC
INTERNAL
MKT. NUMBER
HS0-5104ARH-Q
HS1-5104ARH-Q
HS9-5104ARH-Q
TEMP. RANGE
(
o
C)
25
-55 to 125
-55 to 125
-55 to 125
HS1-5104ARH/PROTO HS1-5104ARH/PROTO
Pinouts
HS-5104ARH (SBDIP) CDIP2-T14
TOP VIEW
OUT 1
-IN1
+IN1
V+
+IN2
-IN2
OUT 2
1
2
3
4
5
6
7
14
13
12
11
10
9
8
OUT 4
-IN4
+IN4
V-
+IN3
-IN3
OUT 3
OUT 1
-IN1
+IN1
V+
+IN2
-IN2
OUT 2
HS-5104ARH (FLATPACK) CDFP3-F14
TOP VIEW
1
2
3
4
5
6
7
14
13
12
11
10
9
8
OUT 4
-IN4
+IN4
V-
+IN3
-IN3
OUT 3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
HS-5104ARH
Burn-In Circuit
1
2
R1
3
+V
C1
4
D1
R2
5
6
7
+
2
3
+
1
4
+
14
Irradiation Circuit
+15V
R4
12
11
R3
10
9
8
D2
C2
-V
-
+
-
13
+
-15V
(ONE OF FOUR)
-
-
-
NOTES:
5. +V = 15V
6. -V = -15V
7. Group E Sample Size = 4 Die Per Wafer
NOTES:
1. R1 = R2 = R3 = R4 = 1MW, 5%, 1/4W (Min)
2. C1 = C2 = 0.01µF/Socket (Min) or 0.1µF/Row (Min)
3. D1 = D2 = IN4002 or Equivalent/Board
4. |(V+) - (V-)| = 31V
±1V
2
HS-5104ARH
Die Characteristics
DIE DIMENSIONS:
95 mils x 99 mils x 19 mils
±1
mils
(2420µm x 2530µm x 483µm
±25.4µm)
INTERFACE MATERIALS:
Glassivation:
Type: Nitride (SI3N4) over Silox (SIO2, 5% Phos.)
Silox Thickness: 12k
Å
±2k
Å
Nitride Thickness: 3.5k
Å
±1.5k
Å
Top Metallization:
Type: Al, 1% Cu
Thickness: 16k
Å
±2k
Å
Substrate:
Bipolar Dielectric Isolation
Backside Finish:
Silicon
ASSEMBLY RELATED INFORMATION:
Substrate Potential
(Powered Up):
Unbiased
ADDITIONAL INFORMATION:
Worst Case Current Density:
<2.0 x 10
5
A/cm
2
Transistor Count:
175
Metallization Mask Layout
HS-5104ARH
+IN2
V+
+IN1
-IN2
-IN1
OUT2
OUT3
OUT1
OUT4
-IN3
-IN4
+IN3
V-
+IN4
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site
http://www.intersil.com
3
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