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HS1-1412RH-Q

QUAD BUFFER AMPLIFIER, CDIP14, SIDE BRAZED, CERAMIC, DIP-14

器件类别:模拟混合信号IC    放大器电路   

厂商名称:Renesas(瑞萨电子)

厂商官网:https://www.renesas.com/

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器件参数
参数名称
属性值
是否Rohs认证
不符合
厂商名称
Renesas(瑞萨电子)
零件包装代码
DIP
包装说明
DIP, DIP14,.3
针数
14
Reach Compliance Code
not_compliant
ECCN代码
EAR99
放大器类型
BUFFER
标称带宽 (3dB)
340 MHz
25C 时的最大偏置电流 (IIB)
25 µA
最大输入失调电压
20000 µV
JESD-30 代码
R-CDIP-T14
JESD-609代码
e0
负供电电压上限
-6 V
标称负供电电压 (Vsup)
-5 V
功能数量
4
端子数量
14
最高工作温度
125 °C
最低工作温度
-55 °C
最小输出电流
0.05 A
封装主体材料
CERAMIC, METAL-SEALED COFIRED
封装代码
DIP
封装等效代码
DIP14,.3
封装形状
RECTANGULAR
封装形式
IN-LINE
峰值回流温度(摄氏度)
NOT SPECIFIED
电源
+-5 V
认证状态
Not Qualified
筛选级别
MIL-PRF-38535 Class V
座面最大高度
5.08 mm
标称压摆率
1155 V/us
供电电压上限
6 V
标称供电电压 (Vsup)
5 V
表面贴装
NO
技术
BIPOLAR
温度等级
MILITARY
端子面层
Tin/Lead (Sn/Pb)
端子形式
THROUGH-HOLE
端子节距
2.54 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
NOT SPECIFIED
总剂量
300k Rad(Si) V
宽度
7.62 mm
文档预览
HS-1412RH
Data Sheet
August 1999
File Number
4230.1
Radiation Hardened, Quad, High Speed,
Low Power, Video Closed Loop Buffer
The HS-1412RH is a radiation hardened quad closed loop
buffer featuring user programmable gain and high speed
performance. Manufactured on Intersil’s proprietary
complementary bipolar UHF-1 (DI bonded wafer) process,
this device offers wide -3dB bandwidth of 340MHz, very fast
slew rate, excellent gain flatness and high output current.
These devices are QML approved and are processed and
screened in full compliance with MIL-PRF-38535.
A unique feature of the pinout allows the user to select a
voltage gain of +1, -1, or +2, without the use of any external
components. Gain selection is accomplished via
connections to the inputs, as described in the “Application
Information” section. The result is a more flexible product,
fewer part types in inventory, and more efficient use of board
space.
Compatibility with existing op amp pinouts provides flexibility
to upgrade low gain amplifiers, while decreasing component
count. Unlike most buffers, the standard pinout provides an
upgrade path should a higher closed loop gain be needed at
a future date.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-96834. A “hot-link” is provided
on our homepage for downloading.
www.intersil.com/spacedefense/space.asp
Features
• Electrically Screened to SMD # 5962-96834
• QML Qualified per MIL-PRF-38535 Requirements
• MIL-PRF-38535 Class V Compliant
• User Programmable For Closed-Loop Gains of +1, -1 or
+2 Without Use of External Resistors
• Standard Operational Amplifier Pinout
• Low Supply Current . . . . . . . . . . . . 5.9mA/Op Amp (Typ)
• Excellent Gain Accuracy . . . . . . . . . . . . . . . 0.99V/V (Typ)
• Wide -3dB Bandwidth. . . . . . . . . . . . . . . . . .340MHz (Typ)
• Fast Slew Rate . . . . . . . . . . . . . . . . . . . . . .1155V/µs (Typ)
• High Input Impedance . . . . . . . . . . . . . . . . . . . 1MΩ (Typ)
• Excellent Gain Flatness (to 50MHz). . . . . .
±0.02dB
(Typ)
• Fast Overdrive Recovery . . . . . . . . . . . . . . . . <10ns (Typ)
• Total Gamma Dose. . . . . . . . . . . . . . . . . . . . 300kRAD(Si)
• Latch Up . . . . . . . . . . . . . . . . . . . . . None (DI Technology)
Applications
• Flash A/D Driver
• Video Switching and Routing
• Pulse and Video Amplifiers
• Wideband Amplifiers
• RF/IF Signal Processing
• Imaging Systems
Ordering Information
ORDERING NUMBER
5962F9683401VCA
5962F9683401VCC
INTERNAL
MKT. NUMBER
HS1-1412RH-Q
HS1B-1412RH-Q
TEMP. RANGE
(
o
C)
-55 to 125
-55 to 125
Pinout
HS-1412RH (CERDIP) GDIP1-T14
OR
HS-1412RH (SBDIP) CDIP2-T14
TOP VIEW
OUT1 1
-IN1 2
+IN1 3
V+ 4
+IN2 5
-IN2 6
OUT2 7
14 OUT4
13 -IN4
12 +IN4
11 V-
10 +IN3
9 -IN3
8 OUT3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
HS-1412RH
Application Information
HS-1412RH Advantages
The HS-1412RH features a novel design which allows the
user to select from three closed loop gains, without any
external components. The result is a more flexible product,
fewer part types in inventory, and more efficient use of board
space. Implementing a quad, gain of 2, cable driver with this
IC eliminates the eight gain setting resistors, which frees up
board space for termination resistors.
Like most newer high performance amplifiers, the HS-1412RH
is a current feedback amplifier (CFA). CFAs offer high
bandwidth and slew rate at low supply currents, but can be
difficult to use because of their sensitivity to feedback
capacitance and parasitics on the inverting input (summing
node). The HS-1412RH eliminates these concerns by bringing
the gain setting resistors on-chip. This yields the optimum
placement and value of the feedback resistor, while minimizing
feedback and summing node parasitics. Because there is no
access to the summing node, the PCB parasitics do not impact
performance at gains of +2 or -1 (see “Unity Gain
Considerations” for discussion of parasitic impact on unity gain
performance).
The HS-1412RH’s closed loop gain implementation provides
better gain accuracy, lower offset and output impedance,
and better distortion compared with open loop buffers.
Unity Gain Considerations
Unity gain selection is accomplished by floating the -Input of
the HS-1412RH. Anything that tends to short the -Input to
GND, such as stray capacitance at high frequencies, will
cause the amplifier gain to increase toward a gain of +2. The
result is excessive high frequency peaking, and possible
instability. Even the minimal amount of capacitance
associated with attaching the -Input lead to the PCB results
in approximately 6dB of gain peaking. At a minimum this
requires due care to ensure the minimum capacitance at the
-Input connection.
Table 1 lists five alternate methods for configuring the
HS-1412RH as a unity gain buffer, and the corresponding
performance. The implementations vary in complexity and
involve performance trade-offs. The easiest approach to
implement is simply shorting the two input pins together,
and applying the input signal to this common node. The
amplifier bandwidth decreases from 550MHz to 370MHz,
but excellent gain flatness is the benefit. A drawback to this
approach is that the amplifier input noise voltage and input
offset voltage terms see a gain of +2, resulting in higher
noise and output offset voltages. Alternately, a 100pF
capacitor between the inputs shorts them only at high
frequencies, which prevents the increased output offset
voltage but delivers less gain flatness.
Another straightforward approach is to add a 620Ω resistor
in series with the amplifier’s positive input. This resistor and
the HS-1412RH input capacitance form a low pass filter
which rolls off the signal bandwidth before gain peaking
occurs. This configuration was employed to obtain the data
sheet AC and transient parameters for a gain of +1.
Closed Loop Gain Selection
This “buffer” operates in closed loop gains of -1, +1, or +2,
with gain selection accomplished via connections to the
±inputs.
Applying the input signal to +IN and floating -IN
selects a gain of +1 (see next section for layout caveats),
while grounding -IN selects a gain of +2. A gain of -1 is
obtained by applying the input signal to -IN with +IN
grounded through a 50Ω resistor.
The table below summarizes these connections:
CONNECTIONS
GAIN
(A
CL
)
-1
+1
+2
+INPUT
50
to GND
Input
Input
-INPUT
Input
NC (Floating)
GND
Pulse Overshoot
The HS-1412RH utilizes a quasi-complementary output stage
to achieve high output current while minimizing quiescent
supply current. In this approach, a composite device replaces
the traditional PNP pulldown transistor. The composite device
switches modes after crossing 0V, resulting in added
distortion for signals swinging below ground, and an
increased overshoot on the negative portion of the output
waveform (see Figure 5, Figure 7, and Figure 9). This
overshoot isn’t present for small bipolar signals (see Figure 4,
Figure 6, and Figure 8) or large positive signals. Figure 28
through Figure 31 illustrate the amplifier’s overshoot
dependency on input transition time, and signal polarity.
TABLE 1. UNITY GAIN PERFORMANCE FOR VARIOUS IMPLEMENTATIONS
APPROACH
Remove -IN Pin
+R
S
= 620Ω
+R
S
= 620Ω and Remove -IN Pin
Short +IN to -IN (e.g., Pins 2 and 3)
100pF Capacitor Between +IN and -IN
PEAKING (dB)
5.0
1.0
0.7
0.1
0.3
BW (MHz)
550
230
225
370
380
SR (V/µs)
1300
1000
1000
500
550
±0.1dB
GAIN FLATNESS (MHz)
18
25
28
170
130
2
HS-1412RH
PC Board Layout
This amplifier’s frequency response depends greatly on the
care taken in designing the PC board (PCB).
The use of low
inductance components such as chip resistors and chip
capacitors is strongly recommended, while a solid
ground plane is a must!
Attention should be given to decoupling the power supplies.
A large value (10µF) tantalum in parallel with a small value
(0.1µF) chip capacitor works well in most cases.
Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance directly on the
output must be minimized, or isolated as discussed in the
next section.
An example of a good high frequency layout is the
Evaluation Board shown in Figure 3.
Evaluation Board
The performance of the HS-1412RH may be evaluated using
the HA5025 Evaluation Board, slightly modified as follows:
1. Remove the four feedback resistors, and leave the
connections open.
2. a. For A
V
= +1 evaluation, remove the gain setting
resistors (R
1
), and leave pins 2, 6, 9, and 13 floating.
b. For A
V
= +2, replace the gain setting resistors (R
1
) with
0Ω resistors to GND.
The modified schematic for amplifier 1, and the board layout
are shown in Figures 2 and 3.
To order evaluation boards (part number HA5025EVAL),
please contact your local sales office.
50Ω
OUT
R
1
(NOTE)
IN
50Ω
1
2
3
4
5
+5V
10µF
0.1µF 6
7
9
8
GND
GND
-
+
14
13
12
11
10
0.1µF
-5V
10µF
NOTE: R
1
=
(A
V
= +1)
or 0Ω (A
V
= +2)
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line will degrade the amplifier’s
phase margin resulting in frequency response peaking and
possible oscillations. In most cases, the oscillation can be
avoided by placing a resistor (R
S
) in series with the output
prior to the capacitance.
Figure 1 details starting points for the selection of this
resistor. The points on the curve indicate the R
S
and C
L
combinations for the optimum bandwidth, stability, and
settling time, but experimental fine tuning is recommended.
Picking a point above or to the right of the curve yields an
overdamped response, while points below or left of the curve
indicate areas of underdamped performance.
50
SERIES OUTPUT RESISTANCE (Ω)
FIGURE 2. MODIFIED EVALUATION BOARD SCHEMATIC
40
30
20
A
V
= +2
10
A
V
= +1
FIGURE 3A. TOP LAYOUT
0
0
50
100
150
200
250
300
350
400
LOAD CAPACITANCE (pF)
FIGURE 1. RECOMMENDED SERIES RESISTOR vs LOAD
CAPACITANCE
R
S
and C
L
form a low pass network at the output, thus limiting
system bandwidth well below the amplifier bandwidth of
350MHz. By decreasing R
S
as C
L
increases (as illustrated in
the curves), the maximum bandwidth is obtained without
sacrificing stability. In spite of this, bandwidth decreases as
the load capacitance increases. For example, at A
V
= +2,
R
S
= 22Ω, C
L
= 100pF, the overall bandwidth is 125MHz, and
bandwidth drops to 100MHz at R
S
= 12Ω, C
L
= 220pF.
3
FIGURE 3B. BOTTOM LAYOUT
FIGURE 3. EVALUATION BOARD LAYOUT
HS-1412RH
Typical Performance Curves
200
A
V
= +2
150
OUTPUT VOLTAGE (mV)
OUTPUT VOLTAGE (V)
100
50
0
-50
-100
-150
-200
TIME (5ns/DIV.)
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
TIME (5ns/DIV.)
V
SUPPLY
=
±5V,
T
A
= 25
o
C, R
L
= 100Ω, Unless Otherwise Specified
2.0
A
V
= +2
FIGURE 4. SMALL SIGNAL PULSE RESPONSE
FIGURE 5. LARGE SIGNAL PULSE RESPONSE
200
150
OUTPUT VOLTAGE (mV)
100
50
0
-50
-100
-150
-200
TIME (5ns/DIV.)
A
V
= +1
2.0
1.5
OUTPUT VOLTAGE (V)
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
TIME (5ns/DIV.)
A
V
= +1
FIGURE 6. SMALL SIGNAL PULSE RESPONSE
FIGURE 7. LARGE SIGNAL PULSE RESPONSE
200
A
V
= -1
150
OUTPUT VOLTAGE (mV)
OUTPUT VOLTAGE (V)
100
50
0
-50
-100
-150
-200
TIME (5ns/DIV.)
2.0
A
V
= -1
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
TIME (5ns/DIV.)
FIGURE 8. SMALL SIGNAL PULSE RESPONSE
FIGURE 9. LARGE SIGNAL PULSE RESPONSE
4
HS-1412RH
Typical Performance Curves
NORMALIZED GAIN (dB)
6
3
A
V
= +2
0
-3
-6
PHASE
A
V
= -1
PHASE (DEGREES)
A
V
= +1
A
V
= +2
0
90
A
V
= -1
A
V
= +1
0.3
1
10
FREQUENCY (MHz)
100
180
270
500
GAIN
V
OUT
= 200mV
P-P
GAIN (dB)
V
SUPPLY
=
±5V,
T
A
= 25
o
C, R
L
= 100Ω, Unless Otherwise Specified
(Continued)
A
V
= +2, V
OUT
= 200mV
P-P
9
6
3
0
GAIN
R
L
= 1kΩ
R
L
= 100Ω
R
L
= 50Ω
0
R
L
= 1kΩ
R
L
= 100Ω
R
L
= 50Ω
90
180
270
100
500
PHASE (DEGREES)
PHASE (DEGREES)
PHASE (DEGREES)
PHASE
0.3
1
10
FREQUENCY (MHz)
FIGURE 10. FREQUENCY RESPONSE
FIGURE 11. FREQUENCY RESPONSE FOR VARIOUS LOAD
RESISTORS
3
GAIN (dB)
0
A
V
= +1, V
OUT
= 200mV
P-P
3
GAIN (dB)
GAIN
0
-3
-6
A
V
= -1, V
OUT
= 200mV
P-P
GAIN
R
L
= 1kΩ
R
L
=100Ω
R
L
= 50Ω
180
90
R
L
= 1kΩ
R
L
= 100Ω
R
L
= 50Ω
0
-90
500
-3
-6
R
L
= 1kΩ
R
L
= 100Ω
R
L
= 50Ω
0
PHASE
90
R
L
= 1kΩ
R
L
= 100Ω
R
L
= 50Ω
0.3
1
10
FREQUENCY (MHz)
100
180
270
500
PHASE (DEGREES)
PHASE
0.3
1
10
FREQUENCY (MHz)
100
FIGURE 12. FREQUENCY RESPONSE FOR VARIOUS LOAD
RESISTORS
FIGURE 13. FREQUENCY RESPONSE FOR VARIOUS LOAD
RESISTORS
9
GAIN (dB)
6
3
0
A
V
= +2
GAIN (dB)
A
V
= +1
3
0
-3
-6
1V
P-P
2.5V
P-P
4V
P-P
PHASE
1V
P-P
2.5V
P-P
4V
P-P
0.3
1
10
FREQUENCY (MHz)
100
0
90
180
270
360
500
GAIN
GAIN
1V
P-P
2.5V
P-P
4V
P-P
PHASE (DEGREES)
PHASE
1V
P-P
2.5V
P-P
4V
P-P
0
90
180
270
100
360
500
0.3
1
10
FREQUENCY (MHz)
FIGURE 14. FREQUENCY RESPONSE FOR VARIOUS OUTPUT
VOLTAGES
FIGURE 15. FREQUENCY RESPONSE FOR VARIOUS OUTPUT
VOLTAGES
5
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