1. The above test circuits are utilized for all package types.
2. The Dynamic Test Circuit is utilized for all life testing.
NOTES:
R = 1kΩ
±5%,
1
/
4
W.
C
1
= C
2
= 0.01µF minimum, 1 each per socket, minimum.
V
S
+ = 15.5V
±0.5V,
V
S
- = -15.5V
±0.5V,
V
R
= 15.5
±0.5V.
FIGURE 2. STATIC BURN-IN TEST CIRCUIT
Irradiation Circuit
HS-1840ARH
+15V
NC
NC
+1V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
-15V
1kΩ
+5V
NOTE:
3. All irradiation testing is performed in the 28 lead CERDIP package.
3
HS-1840ARH
Die Characteristics
DIE DIMENSIONS:
(2820µm x 4080µm x 483µm
±25.4µm)
111 mils x 161 mils x 19 mils
±1
mil
INTERFACE MATERIALS:
Glassivation:
Type: PSG (Phosphorus Silicon Glass)
Thickness: 8.0k
Å
±1k
Å
Top Metallization:
Type: AlSiCu
Thickness: 16.0k
Å
±2k
Å
Backside Finish:
Silicon
ASSEMBLY RELATED INFORMATION:
Substrate Potential:
Unbiased (DI)
ADDITIONAL INFORMATION:
Worst Case Current Density:
Modified SEM
Transistor Count:
407
Process:
Radiation Hardened Silicon Gate,
Bonded Wafer, Dielectric Isolation
Metallization Mask Layout
HS-1840ARH
IN7
IN6
IN5
IN4
IN3
IN2
IN1
IN8
ENABLE
A0
-V
A1
OUT
A2
+V
A3
V
REF
IN16
GND
IN15
IN14
IN13
IN12
IN11
All Intersil semiconductor products are manufactured, assembled and tested under
ISO9000
quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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