Rad-Hard 16 Channel CMOS Analog Multiplexer
with High-Z Analog Input Protection
HS-1840ARH, HS-1840BRH
The HS-1840ARH, HS-1840BRH are radiation hardened,
monolithic 16 channel multiplexers constructed with the
Intersil Rad-Hard Silicon Gate, bonded wafer, Dielectric
Isolation process. They are designed to provide a high input
impedance to the analog source if device power fails
(open), or the analog signal voltage inadvertently exceeds
the supply by up to
±35V,
regardless of whether the device
is powered on or off. Excellent for use in redundant
applications, since the secondary device can be operated in
a standby unpowered mode affording no additional power
drain. More significantly, a very high impedance exists
between the active and inactive devices preventing any
interaction. One of sixteen channel selections is controlled
by a 4-bit binary address plus an Enable-Inhibit input which
conveniently controls the ON/OFF operation of several
multiplexers in a system. All inputs have electrostatic
discharge protection. The HS-1840ARH, HS-1840BRH are
processed and screened in full compliance with
MIL-PRF-38535 and QML standards. The devices are
available in a 28 Ld SBDIP and a 28 Ld Ceramic Flatpack.
Specifications for Rad Hard QML devices are
controlled by the Defense Supply Center in
Columbus (DSCC). The SMD numbers listed here
must be used when ordering.
Detailed Electrical Specifications for these devices
are contained in SMD 5962-95630. A “hot-link” is
provided on our homepage for downloading.
http://www.intersil.com/spacedefense/space.htm
HS-1840ARH, HS-1840BRH
Features
• Electrically Screened to SMD # 5962-95630
• QML Qualified per MIL-PRF-38535 Requirements
• Pin-to-Pin for Intersil’s HS-1840RH and HS-1840/883S
• Improved Radiation Performance
- Gamma Dose (γ) 3x10
5
RAD(Si)
• Improved r
DS(ON)
Linearity
• Improved Access Time 1.5µs (Max) Over Temp and
Post Rad
• High Analog Input Impedance 500MΩ During Power
Loss (Open)
•
±35V
Input Overvoltage Protection (Power On or Off)
• Dielectrically Isolated Device Islands
• Excellent in Hi-Rel Redundant Systems
• Break-Before-Make Switching
• No Latch-Up
Ordering Information
ORDERING
NUMBER
5962F9563002QXC
5962F9563002QYC
5962F9563002VXC
5962F9563002VYC
HS1-1840ARH/PROTO
HS9-1840ARH/PROTO
HS1-1840ARH-T
5962F9563002V9A
5962F9563003QXC
INTERNAL
MKT. NUMBER
HS1-1840ARH-8
HS9-1840ARH-8
HS1-1840ARH-Q
HS9-1840ARH-Q
HS1-1840ARH/PROTO
HS9-1840ARH/PROTO
HS1-1840ARH-T
HS0-1840ARH-Q
HS1-1840BRH-8
TEMP. RANGE
(°C)
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
Q 5962F95 63003QXC
28 Ld SBDIP
PART
MARKING NO.
Q 5962F95 63002QXC
Q 5962F95 63002QYC
Q 5962F95 63002VXC
Q 5962F95 63002VYC
HS1- 1840ARH /PROTO
HS9- 1840ARH /PROTO
Q 5962R95 63002TXC
PACKAGE
28 Ld SBDIP
28 Ld Flatpack
28 Ld SBDIP
28 Ld Flatpack
28 Ld SBDIP
28 Ld Flatpack
28 Ld SBDIP
September 14, 2010
FN4355.3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002, 2009, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HS-1840ARH, HS-1840BRH
Ordering Information
(Continued)
ORDERING
NUMBER
5962F9563003QYC
5962F9563003VXC
5962F9563003VYC
HS1-1840BRH/PROTO
HS9-1840BRH/PROTO
5962F9563003V9A
INTERNAL
MKT. NUMBER
HS9-1840BRH-8
HS1-1840BRH-Q
HS9-1840BRH-Q
HS1-1840BRH/PROTO
HS9-1840BRH/PROTO
HS0-1840BRH-Q
TEMP. RANGE
(°C)
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
PART
MARKING NO.
Q 5962F95 63003QYC
Q 5962F95 63003VXC
Q 5962F95 63003VYC
HS1- 1840BRH /PROTO
HS9- 1840BRH /PROTO
PACKAGE
28 Ld Flatpack
28 Ld SBDIP
28 Ld Flatpack
28 Ld SBDIP
28 Ld Flatpack
Pin Configurations
HS1-1840ARH, HS1-1840BRH
(28 LD SBDIP) CDIP2-T28
TOP VIEW
+V
S
1
NC 2
NC 3
IN 16 4
IN 15 5
IN 14 6
IN 13 7
IN 12 8
IN 11 9
IN 10 10
IN 9 11
GND 12
(+5V
S
) V
REF
13
ADDR A3 14
28 OUT
27 -V
S
26 IN 8
25 IN 7
24 IN 6
23 IN 5
22 IN 4
21 IN 3
20 IN 2
19 IN 1
18 ENABLE
17 ADDR A0
16 ADDR A1
15 ADDR A2
+V
S
NC
NC
IN 16
IN 15
IN 14
IN 13
IN 12
IN 11
IN 10
IN 9
GND
(+5V
S
) V
REF
ADDR A3
HS9-1840ARH, HS9-1840BRH
(28 LD FLATPACK) CDFP3-F28
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OUT
-V
S
IN 8
IN 7
IN 6
IN 5
IN 4
IN 3
IN 2
IN 1
ENABLE
ADDR A0
ADDR A1
ADDR A2
2
FN4355.3
September 14, 2010
HS-1840ARH, HS-1840BRH
Functional Diagram
V
DD
A0
IN1
1
A1
DIGITAL
ADDRESS
A2
MAINSWITCH 1
A3
OUT
IN16
EN
16
MAINSWITCH 16
ADDRESS INPUT
BUFFER AND
LEVEL SHIFTER
DECODERS
MULTIPLEX
SWITCHES
NOTE: MAINSWITCH INXX: SWITCH ON, BODY TIED TO SOURCE
SWITCH OFF, BODY TIED TO VCC-0.7V
TABLE 1. TRUTH TABLE
A3
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
A2
X
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
A1
X
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
A0
X
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
EN
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
“ON” CHANNEL
None
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
3
FN4355.3
September 14, 2010
HS-1840ARH, HS-1840BRH
Burn-In/Life Test Circuits
R
+V
S
R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
F3
F5
F1
F2
GND
V
R
R
-V
S
+V
S
R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R
-V
S
R
GND
F4
R
NOTE:
V
S
+ = +15.5V
±0.5V,
V
S
- = -15.5V
±0.5V.
R = 1kΩ
±5%.
C
1
= C
2
= 0.01µF
±10%,
1 EACH PER SOCKET, MINIMUM.
D
1
= D
2
= 1N4002, 1 EACH PER BOARD, MINIMUM.
INPUT SIGNALS:
SQUARE WAVE, 50% DUTY CYCLE, 0V TO 15V PEAK
±10%.
F1 = 100kHz; F2 = F1/2; F3 = F1/4; F4 = F1/8; F5 = F1/16.
NOTE:
R = 1kΩ
±5%,
1/4W.
C
1
= C
2
= 0.01µF MINIMUM, 1 EACH PER SOCKET, MINIMUM.
V
S
+ = 15.5V
±0.5V,
V
S
- = -15.5V
±0.5V,
V
R
= 15.5
±0.5V
FIGURE 1. DYNAMIC BURN-IN AND LIFE TEST CIRCUIT
NOTES:
1. The above test circuits are utilized for all package types.
2. The Dynamic Test Circuit is utilized for all life testing.
FIGURE 2. .STATIC BURN-IN TEST CIRCUIT
Irradiation Circuit
HS-1840ARH, HS-1840BRH
+15V
NC
NC
+1V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
+5V
28
27
26
25
24
23
22
21
20
19
18
17
16
15
-15V
1kΩ
NOTE:
3. All irradiation testing is performed in the 28 lead CERDIP package.
4
FN4355.3
September 14, 2010
HS-1840ARH, HS-1840BRH
Die Characteristics
DIE DIMENSIONS:
(2820µmx4080µm x 483µm
±25.4μm)
111 milsx161 milsx19 mils
±1
mil
INTERFACE MATERIALS:
Glassivation:
Type: PSG (Phosphorus Silicon Glass)
Thickness: 8.0k
Å
±1k
Å
Top Metallization:
Type: AlSiCu
Thickness: 16.0k
Å
±2k
Å
Backside Finish:
Silicon
ASSEMBLY RELATED INFORMATION:
Substrate Potential:
Unbiased (DI)
ADDITIONAL INFORMATION:
Worst Case Current Density:
Modified SEM
Transistor Count:
407
Process:
Radiation Hardened Silicon Gate,
Bonded Wafer, Dielectric Isolation
Metallization Mask Layout
HS-1840ARH, HS-1840BRH
IN7
IN6
IN5
IN4
IN3
IN2
IN1
IN8
ENABLE
A0
-V
A1
OUT
A2
+V
A3
V
REF
IN16
GND
IN15
IN14
IN13
IN12
IN11
IN10
IN9
5
FN4355.3
September 14, 2010
