• Wide analog voltage range (±15V supplies) . . . . . . . . . . . . ±15V
• TTL compatible
Applications
• High speed multiplexing
• Sample and hold circuits
• Digital filters
• Operational amplifier gain switching networks
Integrator reset circuits
Pin Configuration
HS1-201HSRH, HS1-201HSEH SBDIP (CDIP2-T16)
HS9-201HSRH, HS9-201HSEH FLATPACK (CDFP4-F16)
TOP VIEW
A1 1
OUT1 2
IN1 3
V- 4
GND 5
IN4 6
OUT4 7
A4 8
16 A2
15 OUT2
14 IN2
13 V+
12 NC
11 IN3
10 OUT3
9 A3
June 24, 2013
FN4874.2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Copyright Intersil Americas LLC 2000, 2006, 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
HS-201HSRH, HS-201HSEH
Ordering Information
ORDERING
SMD NUMBER
(Note 3)
5962F9961801VEC
5962F9961802VEC
5962F9961801QEC
5962F9961801VXC
5962F9961802VXC
5962F9961801QXC
5962F9961801V9A
5962F9961802V9A
HS1-201HSRH/PROTO
HS9-201HSRH/PROTO
HS0-201HSRH/SAMPLE
INTERNAL
MKT. NUMBER
(Notes 1, 2)
HS1-201HSRH-Q
HS1-201HSEH-Q
HS1-201HSRH-8
HS9-201HSRH-Q
HS9-201HSEH-Q
HS9-201HSRH-8
HS0-201HSRH-Q
HS0-201HSEH-Q
HS1-201HSRH/PROTO
HS9-201HSRH/PROTO
HS0-201HSRH/SAMPLE
HS1-201HSRH/PROTO
HS9-201HSRH/PROTO
PART
MARKING
Q 5962F99 61801VEC
Q 5962F99 61802VEC
Q 5962F99 61801QEC
Q 5962F99 61801VXC
Q 5962F99 61802VXC
Q 5962F99 61801QXC
TEMP. RANGE
(°C)
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
PACKAGE
(RoHS Compliant)
16 Ld SBDIP
16 Ld SBDIP
16 Ld SBDIP
16 Ld Flatpack
16 Ld Flatpack
16 Ld Flatpack
Die
Die
16 Ld SBDIP
16 Ld Flatpack
Die
D16.3
K16.A
PKG.
DWG. #
D16.3
D16.3
D16.3
K16.A
K16.A
K16.A
NOTE:
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
2. For Moisture Sensitivity Level (MSL), please see device information page for
HS-201HSRH, HS-201HSEH
. For more information on MSL, please see
tech brief
TB363.
3. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in the
“Ordering Information” table on page 2 must be used when ordering
2
FN4874.2
June 24, 2013
HS-201HSRH, HS-201HSEH
Die Characteristics
DIE DIMENSIONS
2790µm x 4950µm (110 mils x 195 mils)
Thickness: 483µm ±25.4µm (19 mils ±1 mil)
ASSEMBLY RELATED INFORMATION
Substrate Potential
Unbiased (DI)
ADDITIONAL INFORMATION
Worst Case Current Density
<2.0 x 10
5
A/cm
2
Transistor Count
328
INTERFACE MATERIALS
Glassivation
Type: Phosphorus Silicon Glass (PSG)
Thickness: 8.0k
Å
±1.0k
Å
Metallization
Type: Ti/AlCu
Thickness: 16.0k
Å
± 2k
Å
Substrate
Rad Hard Silicon Gate, Dielectric Isolation
Backside Finish
Silicon
Metallization Mask Layout
OUT4
IN4
GND
V-
IN1
OUT1
A4
A1
A3
A2
OUT3
IN3
V+
IN2
OUT2
3
FN4874.2
June 24, 2013
HS-201HSRH, HS-201HSEH
Package Outline Drawing
K16.A
16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
Rev 2, 1/10
0.015 (0.38)
0.008 (0.20)
PIN NO. 1
ID OPTIONAL
1
2
0.050 (1.27 BSC)
PIN NO. 1
ID AREA
0.440 (11.18)
MAX
0.005 (0.13)
MIN
4
0.022 (0.56)
0.015 (0.38)
TOP VIEW
0.115 (2.92)
0.045 (1.14)
0.045 (1.14)
0.026 (0.66)
6
0.285 (7.24)
0.245 (6.22)
0.009 (0.23)
0.004 (0.10)
-D-
-H-
-C-
0.13 (3.30)
MIN
0.370 (9.40)
0.250 (6.35)
SEATING AND
BASE PLANE
0.03 (0.76) MIN
LEAD FINISH
SIDE VIEW
NOTES:
1. Index area: A notch or a pin one identification mark shall be located
adjacent to pin one and shall be located within the shaded area shown.
The manufacturer’s identification shall not be used as a pin one
identification mark. Alternately, a tab may be used to identify pin one.
2. If a pin one identification mark is used in addition to a tab, the limits
of the tab dimension do not apply.
3. The maximum limits of lead dimensions (section A-A) shall be
measured at the centroid of the finished lead surfaces, when solder
dip or tin plate lead finish is applied.
4. Measure dimension at all four corners.
5. For bottom-brazed lead packages, no organic or polymeric materials
shall be molded to the bottom of the package to cover the leads.
3
SECTION A-A
6. Dimension shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension minimum shall
be reduced by 0.0015 inch (0.038mm) maximum when solder dip
lead finish is applied.
7. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
8. Controlling dimension: INCH.
0.006 (0.15)
0.004 (0.10)
LEAD FINISH
BASE
METAL
0.019 (0.48)
0.015 (0.38)
0.0015 (0.04)
MAX
0.009 (0.23)
0.004 (0.10)
0.022 (0.56)
0.015 (0.38)
4
FN4874.2
June 24, 2013
HS-201HSRH, HS-201HSEH
Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
c1
-A-
-D-
BASE
METAL
b1
M
(b)
SECTION A-A
(c)
LEAD FINISH
D16.3
MIL-STD-1835 CDIP2-T16 (D-2, CONFIGURATION C)
16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
INCHES
SYMBOL
A
b
b1
b2
b3
MIN
-
0.014
0.014
0.045
0.023
0.008
0.008
-
0.220
MAX
0.200
0.026
0.023
0.065
0.045
0.018
0.015
0.840
0.310
MILLIMETERS
MIN
-
0.36
0.36
1.14
0.58
0.20
0.20
-
5.59
MAX
5.08
0.66
0.58
1.65
1.14
0.46
0.38
21.34
7.87
2.54 BSC
7.62 BSC
3.81 BSC
3.18
0.38
0.13
0.13
90
o
-
-
-
-
16
5.08
1.52
-
-
105
o
0.38
0.76
0.25
0.038
NOTES
-
2
3
-
4
2
3
-
-
-
-
-
-
5
6
7
-
-
-
-
2
8
Rev. 0 4/94
E
M
-B-
bbb S C A - B S
BASE
PLANE
SEATING
PLANE
S1
b2
b
A A
D
S2
-C-
Q
A
L
D S
c
c1
e
A
D
E
e
eA
eA/2
L
Q
S1
S2
e
e
A/2
c
0.100 BSC
0.300 BSC
0.150 BSC
0.125
0.015
0.005
0.005
90
o
-
-
-
-
16
0.200
0.060
-
-
105
o
0.015
0.030
0.010
0.0015
ccc M C A - B S D S
aaa
M C A - B S D S
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. Dimension Q shall be measured from the seating plane to the
base plane.
6. Measure dimension S1 at all four corners.
7. Measure dimension S2 from the top of the ceramic body to the
nearest metallization or lead.
8. N is the maximum number of terminal positions.
9. Braze fillets shall be concave.
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
11. Controlling dimension: INCH.
α
aaa
bbb
ccc
M
N
For additional products, see
www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at
www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see
