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HS9-302RH-8

Analog Switch ICs

器件类别:半导体    其他集成电路(IC)   

厂商名称:Intersil ( Renesas )

厂商官网:http://www.intersil.com/cda/home/

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器件:HS9-302RH-8

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器件参数
参数名称
属性值
产品种类
Product Category
Analog Switch ICs
制造商
Manufacturer
Intersil ( Renesas )
Number of Switches
2 Switch
Configuration
2 x SPDT
On Resistance - Max
60 Ohms
On Time - Max
500 ns
Off Time - Max
450 ns
工作电源电压
Operating Supply Voltage
+/- 15 V
最大工作温度
Maximum Operating Temperature
+ 125 C
封装 / 箱体
Package / Case
CFPAK
高度
Height
2.92 mm (Max)
长度
Length
9.91 mm (Max)
Maximum Dual Supply Voltage
+/- 22 V
最小工作温度
Minimum Operating Temperature
- 55 C
Pd-功率耗散
Pd - Power Dissipation
480 mW
Supply Current - Max
0.5 mA
Supply Type
Dual Supply
宽度
Width
6.6 mm (Max)
文档预览
DATASHEET
Radiation Hardened CMOS Dual SPDT Analog Switch
HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH
The HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH analog
Features
switches are monolithic devices fabricated using Intersil’s
dielectrically isolated Radiation Hardened Silicon Gate (RSG)
process technology to insure latch-up free operation. They are
pinout compatible and functionally equivalent to the
HS-303RH, but offer improved 300kRAD(Si) total dose
capability. These switches offers low-resistance switching
performance for analog voltages up to the supply rails.
ON-resistance is low and stays reasonably constant over the
full range of operating voltage and current. ON-resistance also
stays reasonably constant when exposed to radiation.
Break-before-make switching is controlled by 5V digital inputs.
The HS-303ARH, HS-303AEH should be operated with nominal
±15V supplies, while the HS-303BRH, HS-303BEH should be
operated with nominal ±12V supplies.
• QML, per MIL-PRF-38535
• Radiation performance
- Total dose: 3x10
5
rad(Si)
- SEE: For LET = 60MeV-mg/cm
2
at 60° incident angle,
<150pC charge transferred to the output of an off switch
• No latch-up, dielectrically isolated device islands
• Pinout and functionally compatible with Intersil HS-303RH
and HI-303 series analog switches
• Analog signal range equal to the supply voltage range
• Low leakage . . . . . . . . . . . . . . . . . . . . . 100nA (max, post-rad)
• Low r
ON
. . . . . . . . . . . . . . . . . . . . . . . . . . . 70Ω (max, post-rad)
• Low standby supply current . . . . . . . . . . . . . +150µA/-100µA
(max, post-rad)
Specifications
Specifications for Rad Hard QML devices are controlled by the
Defense Logistics Agency Land and Maritime (DLA). The SMD
number listed in the following must be used when ordering.
Detailed Electrical Specifications for the HS-303ARH,
HS-303AEH, HS-303BRH, HS-303BEH are contained in
SMD
5962-95813.
Functional Diagram
IN
N
P
D
Pin Configurations
HS1-303ARH, HS-303BRH
(SBDIP), CDIP2-T14
TOP VIEW
NC
S3
D3
D1
1
2
3
4
5
6
7
14 V+
13 S4
12 D4
11 D2
10 S2
9 IN2
8 V-
TRUTH TABLE
LOGIC
0
1
SW1 AND SW2
OFF
ON
SW3 AND SW4
ON
OFF
S1
IN1
GND
HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH
(FLATPACK) CDFP3-F14
TOP VIEW
NC
S3
D3
D1
S1
IN1
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V+
S4
D4
D2
S2
IN2
V-
March 4, 2015
FN6411.3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Copyright Intersil Americas Inc. 2006, 2008, 2012, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH
Ordering Information
ORDERING NUMBER
(Note
2)
5962F9581304QCC
5962F9581304QXC
5962F9581304V9A
5962F9581306V9A
5962F9581304VCC
5962F9581306VCC
5962F9581304VXC
HS0-303ARH/SAMPLE
HS1-303ARH/PROTO
HS9-303ARH/PROTO
5962F9581306VXC
5962F9581305QCC
5962F9581305QXC
5962F9581305V9A
5962F9581307V9A
5962F9581305VCC
5962F9581307VCC
5962F9581305VXC
HS0-303BRH/SAMPLE
HS1-303BRH/PROTO
HS9-303BRH/PROTO
5962F9581307VXC
NOTES:
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in the
“Ordering Information” table must be used when ordering.
PART NUMBER
(Note
1)
HS1-303ARH-8
HS9-303ARH-8
HS0-303ARH-Q
HS0-303AEH-Q
HS1-303ARH-Q
HS1-303AEH-Q
HS9-303ARH-Q
HS0-303ARH/SAMPLE
HS1-303ARH/PROTO
HS9-303ARH/PROTO
HS9-303AEH-Q
HS1-303BRH-8
HS9-303BRH-8
HS0-303BRH-Q
HS0-303BEH-Q
HS1-303BRH-Q
HS1-303BEH-Q
HS9-303BRH-Q
HS0-303BRH/SAMPLE
HS1-303BRH/PROTO
HS9-303BRH/PROTO
HS9-303BEH-Q
TEMP. RANGE
(°C)
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
PACKAGE
(RoHS Compliant)
14 LD SBDIP
14 LD Flatpack
Die
Die
14 LD SBDIP
14 LD SBDIP
14 LD Flatpack
Die
14 LD SBDIP
14 LD Flatpack
14 LD Flatpack
14 LD SBDIP
14 LD Flatpack
Die
Die
14 LD SBDIP
14 LD SBDIP
14 LD Flatpack
Die
14 LD SBDIP
14 LD Flatpack
14 LD Flatpack
D14.3
K14.A
K14.A
D14.3
K14.A
K14.A
D14.3
K14.A
D14.3
D14.3
D14.3
D14.3
K14.A
PKG.
DWG. #
D14.3
K14.A
D14.3
D14.3
D14.3
D14.3
K14.A
Submit Document Feedback
2
FN6411.3
March 4, 2015
HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH
Die Characteristics
DIE DIMENSIONS:
2690µm x 5200µm (106mils x 205mils)
Thickness: 483µm ± 25.4µm (19mils ± 1mil)
Substrate:
Radiation Hardened Silicon Gate,
Dielectric Isolation
Backside Finish:
Silicon
INTERFACE MATERIALS:
Glassivation:
Type: PSG (Phosphorous Silicon Glass)
Thickness: 8.0k
Å
± 1.0k
Å
Top Metallization:
Type: AlSiCu
Thickness: 16.0k
Å
± 2k
Å
ASSEMBLY RELATED INFORMATION:
Substrate Potential:
Unbiased (DI)
ADDITIONAL INFORMATION:
Worst Case Current Density:
<2.0 x 10
5
A/cm
2
Transistor Count:
332
Metallization Mask Layout
HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH
IN2
V-
V+
GND
IN1
D4
D2
S4
S2
S1
S3
For additional products, see
www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at
www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see
www.intersil.com
Submit Document Feedback
3
D3
D1
FN6411.3
March 4, 2015
HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH
Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
c1
-A-
-D-
BASE
METAL
M
-B-
bbb S C A - B S
BASE
PLANE
SEATING
PLANE
S1
b2
b
A A
D
S2
-C-
Q
A
L
D S
b1
M
(b)
SECTION A-A
(c)
LEAD FINISH
D14.3
MIL-STD-1835 CDIP2-T14 (D-1, CONFIGURATION C)
14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
INCHES
SYMBOL
A
b
b1
b2
b3
c
c1
D
E
e
eA
eA/2
L
Q
S1
S2
MIN
-
0.014
0.014
0.045
0.023
0.008
0.008
-
0.220
MAX
0.200
0.026
0.023
0.065
0.045
0.018
0.015
0.785
0.310
MILLIMETERS
MIN
-
0.36
0.36
1.14
0.58
0.20
0.20
-
5.59
MAX
5.08
0.66
0.58
1.65
1.14
0.46
0.38
19.94
7.87
2.54 BSC
7.62 BSC
3.81 BSC
3.18
0.38
0.13
0.13
90
o
-
-
-
-
14
5.08
1.52
-
-
105
o
0.38
0.76
0.25
0.038
NOTES
-
2
3
-
4
2
3
-
-
-
-
-
-
5
6
7
-
-
-
-
2
8
Rev. 0 4/94
E
e
A
e
e
A/2
c
0.100 BSC
0.300 BSC
0.150 BSC
0.125
0.015
0.005
0.005
90
o
-
-
-
-
14
0.200
0.060
-
-
105
o
0.015
0.030
0.010
0.0015
ccc M C A - B S D S
aaa
M C A - B S D S
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. Dimension Q shall be measured from the seating plane to the
base plane.
6. Measure dimension S1 at all four corners.
7. Measure dimension S2 from the top of the ceramic body to the
nearest metallization or lead.
8. N is the maximum number of terminal positions.
9. Braze fillets shall be concave.
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
11. Controlling dimension: INCH.
aaa
bbb
ccc
M
N
Submit Document Feedback
4
FN6411.3
March 4, 2015
HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH
Ceramic Metal Seal Flatpack Packages (Flatpack)
A
K14.A
MIL-STD-1835 CDFP3-F14 (F-2A, CONFIGURATION B)
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
INCHES
SYMBOL
MIN
0.045
0.015
0.015
0.004
0.004
-
0.235
-
0.125
0.030
0.008
0.270
0.026
0.005
-
14
MAX
0.115
0.022
0.019
0.009
0.006
0.390
0.260
0.290
-
-
0.015
0.370
0.045
-
0.0015
A
b
b1
c
c1
D
MILLIMETERS
MIN
1.14
0.38
0.38
0.10
0.10
-
5.97
-
3.18
0.76
1.27 BSC
0.20
6.86
0.66
0.13
-
14
0.38
9.40
1.14
-
0.04
MAX
2.92
0.56
0.48
0.23
0.15
9.91
6.60
7.11
-
-
NOTES
-
-
-
-
-
3
-
3
-
7
-
2
-
8
6
-
-
Rev. 0 5/18/94
e
PIN NO. 1
ID AREA
A
-A-
-B-
D
S1
b
E1
0.004 M
Q
A
-C-
-H-
L
E3
SEATING AND
BASE PLANE
c1
LEAD FINISH
E2
E3
L
H A-B S
D S
E
0.036 M
H A-B S
C
-D-
D S
E
E1
E2
E3
e
k
L
Q
S1
M
N
0.050 BSC
BASE
METAL
b1
M
M
(b)
SECTION A-A
(c)
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark. Alternately, a tab (dimension k)
may be used to identify pin one.
2. If a pin one identification mark is used in addition to a tab, the lim-
its of dimension k do not apply.
3. This dimension allows for off-center lid, meniscus, and glass
overrun.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness. The maximum lim-
its of lead dimensions b and c or M shall be measured at the cen-
troid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-brazed lead packages, no organic or polymeric mate-
rials shall be molded to the bottom of the package to cover the
leads.
8. Dimension Q shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension Q minimum
shall be reduced by 0.0015 inch (0.038mm) maximum when sol-
der dip lead finish is applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
Submit Document Feedback
5
FN6411.3
March 4, 2015
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参数对比
与HS9-302RH-8相近的元器件有:HS1-302RH-8。描述及对比如下:
型号 HS9-302RH-8 HS1-302RH-8
描述 Analog Switch ICs Analog Switch ICs
产品种类
Product Category
Analog Switch ICs Analog Switch ICs
制造商
Manufacturer
Intersil ( Renesas ) Intersil ( Renesas )
Number of Switches 2 Switch 2 Switch
Configuration 2 x SPDT 2 x DPST
On Resistance - Max 60 Ohms 60 Ohms
On Time - Max 500 ns 500 ns
Off Time - Max 450 ns 450 ns
工作电源电压
Operating Supply Voltage
+/- 15 V +/- 15 V
最大工作温度
Maximum Operating Temperature
+ 125 C + 125 C
封装 / 箱体
Package / Case
CFPAK SBCDIP
高度
Height
2.92 mm (Max) 3.56 mm (Max)
长度
Length
9.91 mm (Max) 19.94 mm (Max)
Maximum Dual Supply Voltage +/- 22 V +/- 22 V
最小工作温度
Minimum Operating Temperature
- 55 C - 55 C
Pd-功率耗散
Pd - Power Dissipation
480 mW 710 mW
Supply Current - Max 0.5 mA 0.5 mA
Supply Type Dual Supply Dual Supply
宽度
Width
6.6 mm (Max) 7.87 mm (Max)
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