®
HSP43168
Data Sheet
July 27, 2009
FN2808.12
Dual FIR Filter
The HSP43168 Dual FIR Filter consists of two independent
8-tap FIR filters. Each filter supports decimation from 1 to 16
and provides on-board storage for 32 sets of coefficients.
The Block Diagram shows two FIR cells each fed by a
separate coefficient bank and one of two separate inputs.
The outputs of the FIR cells are either summed or
multiplexed by the MUX/Adder. The compute power in the
FIR Cells can be configured to provide quadrature filtering,
complex filtering, 2-D convolution, 1-D/2-D correlations, and
interpolating/decimating filters.
The FIR cells take advantage of symmetry in FIR coefficients
by pre-adding data samples prior to multiplication. This
allows an 8-tap FIR to be implemented using only 4
multipliers per filter cell. These cells can be configured as
either a single 16-tap FIR filter or dual 8-tap FIR filters.
Asymmetric filtering is also supported.
Decimation of up to 16 is provided to boost the effective
number of filter taps from 2 to 16 times. Further, the Decimation
Registers provide the delay necessary for fractional data
conversion and 2-D filtering with kernels to 16x16.
The flexibility of the Dual is further enhanced by 32 sets of
user programmable coefficients. Coefficient selection may
be changed asynchronously from clock to clock. The ability
to toggle between coefficient sets further simplifies
applications such as polyphase or adaptive filtering.
The HSP43168 is a low power fully static design
implemented in an advanced CMOS process. The
configuration of the device is controlled through a standard
microprocessor interface.
Features
• Two Independent 8-Tap FIR Filters Configurable as a
Single 16-Tap FIR
• 10-Bit Data and Coefficients
• On-Board Storage for 32 Programmable Coefficient Sets
• Up To: 256 FIR Taps, 16x16 2-D Kernels, or 10x19-Bit
Data and Coefficients
• Programmable Decimation to 16
• Programmable Rounding on Output
• Standard Microprocessor Interface
• Pb-Free Available (RoHS Compliant)
Applications
• Quadrature, Complex Filtering
• Image Processing
• Polyphase Filtering
• Adaptive Filtering
Ordering Information
PART NUMBER
HSP43168VC-45
HSP43168VC-45Z (Note)
HSP43168JC-33
HSP43168JC-33Z (Note)
PART MARKING
HSP43168VC-45
HSP43168VC-45Z
HSP43168JC-33
HSP43168JC-33Z
TEMP. RANGE
(°C)
0 to +70
0 to +70
0 to +70
0 to +70
PACKAGE
100 Ld MQFP
100 Ld MQFP (Pb-free)
84 Ld PLCC
84 Ld PLCC
PKG.
DWG. #
Q100.14x20
Q100.14x20
N84.1.15
N84.1.15
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2000, 2001, 2004, 2007, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HSP43168
Block Diagram
CIN0 - 9
A0 - 8
WR
CSEL0 - 4
10
9
CONTROL/
CONFIGURATION
COEFFICIENT
BANK A
10
INA0 - 9
FIR CELL A
MUX
MUX /
ADDER
9
OEL
OEH
MUX
COEFFICIENT
BANK B
FIR CELL B
INB0 - 9/
OUT0 - 8
10
19
OUT9 - 27
Pinouts
HSP43168
(84 LD PLCC)
TOP VIEW
CIN 9
CSEL 4
CSEL 3
CSEL 2
CSEL 1
CSEL 0
V
CC
A8
A7
A6
A5
A4
A3
A2
A1
A0
GND
WR
MUX 1
MUX 0
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
INB 8
INB 7
INB 6
INB 5
GND
INB 4
INB 3
INB 2
INB 1
INB 0
OEL
OUT 9
OUT 10
V
CC
OUT 11
OUT 12
OUT 13
OUT 14
OUT 15
OUT 16
GND
CIN 8
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
CIN 7
CIN 6
CIN 5
CIN 4
GND
CIN 3
CIN 2
CIN 1
CIN 0
INA 9
INA 8
INA 7
INA 6
INA 5
V
CC
INA 4
INA 3
INA 2
INA 1
INA 0
INB 9
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RVRS
FWD
SHFTEN
TXFR
ACCEN
V
CC
CLK
GND
OEH
OUT 27
OUT 26
OUT 25
OUT 24
OUT 23
OUT 22
OUT 21
OUT 20
OUT 19
OUT 18
OUT 17
V
CC
2
FN2808.12
July 27, 2009
HSP43168
Pinouts
(Continued)
HSP43168
(100 LD MQFP)
TOP VIEW
CIN9
CSEL4
CSEL3
CSEL2
CSEL1
CSEL0
V
CC
V
CC
A8
A7
A6
A5
A4
A3
A2
A1
A0
GND
GND
WR
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
CIN8
NC
CIN7
NC
CIN6
CIN5
CIN4
GND
GND
CIN3
CIN2
CIN1
CIN0
INA9
INA8
INA7
INA6
INA5
V
CC
V
CC
INA4
INA3
INA2
INA1
INA0
NC
NC
INB9
INB8
INB7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
INB6
INB5
GND
GND
INB4
INB3
INB2
INB1
INB0
OEL
OUT9
OUT10
V
CC
V
CC
OUT11
OUT12
OUT13
OUT14
OUT15
OUT16
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
MUX1
MUX0
RVRS
NC
FWRD
SHIFTEN
TXFR
ACCEN
V
CC
V
CC
CLK
GND
GND
OEH
OUT27
OUT26
OUT25
OUT24
OUT23
OUT22
OUT21
OUT20
OUT19
OUT18
OUT17
NC
V
CC
V
CC
GND
GND
3
FN2808.12
July 27, 2009
HSP43168
Pin Description
SYMBOL
V
CC
GND
CIN0-9
A0-8
I
I
TYPE
V
CC
: +5V power supply pin
Ground
Control/Coefficient Data Bus. Processor interface for loading control data and coefficients. CIN0 is the LSB
Control/Coefficient Address Bus. Processor interface for addressing Control and Coefficient Registers. A0 is the
LSB
Control/Coefficient Write Clock. Data is latched into the Control and Coefficient Registers on the rising edge of WR
Coefficient Select. This input determines which of the 32 coefficient sets are to be used by FIR A and B. This input
is registered and CSEL0 is the LSB.
Input to FIR A. INA0 is the LSB
Bidirectional Input for FIR B. INB0 is the LSB and is input only. When used as output, INB1-9 are the LSBs of the
output bus, and INB9 is the MSB of these bits.
19 MSBs of Output Bus. Data format is either unsigned or two's complement depending on configuration. OUT27
is the MSB.
Shift Enable. This active low input enables clocking of data into the part and shifting of data through the Decimation
Registers.
Forward ALU Input Enable. When active low, data from the forward decimation path is input to the ALUs through
the “a” input. When high, the “a” inputs to the ALUs are zeroed.
Reverse ALU Input Enable. When active low, data from the reverse decimation path is input to the ALUs through
the “b” input. When high, the “b” inputs to the ALUs are zeroed.
Data Transfer Control. This active low input switches the LIFO being read into the reverse decimation path with
the LIFO being written from the forward decimation path (see Figure 1).
Adder/Mux Control. This input controls data flow through the output Adder/Mux. Table 5 lists the various
configurations.
Clock. All inputs except those associated with the processor interface (CIN0-9, A0-8, WR) and the output enables
(OEL, OEH) are registered by the rising edge of CLK.
Output Enable Low. This three-state control enables the LSBs of the output bus to INB1-9 when OEL is low.
Output Enable High. This three-state control enables OUT9-27 when OEH is low.
Accumulate Enable. This active high input allows accumulation in the FIR Cell Accumulator. A low on this input
latches the FIR Accumulator contents into the Output Holding Registers while zeroing the feedback pass in the
Accumulator.
No connect
DESCRIPTION
WR
CSEL0-4
I
I
INA0-9
INB0-9
I
I/O
OUT9-27
O
SHFTEN
I
FWRD
FWD
RVRS
I
I
TXFR
I
MUX0-1
I
CLK
I
OEL
OEH
ACCEN
I
I
I
NC
4
FN2808.12
July 27, 2009
1
TXFR
DELAY 4
0
DELAY 3
FIR A REVERSE PATH
M
U
X
†
DATA REVERSAL ENABLE
DATA FEEDBACK
CIRCUITRY
1
DELAY 4
DELAY 3
0
M
U
X
†
FIR A ODD/EVEN # TAPS
DECIMATION REGISTERS
M
U
X
LIFO A
LIFO B
DELAY
1-16
††
D
E M
M U
U X
X
†
ODD/EVEN SYMMETRY
†
MODE SELECT
†
FIR B
ODD/EVEN # TAPS
DECIMATION REGISTERS
M
U
X
DATA FEEDBACK
CIRCUITRY
LIFO A
LIFO B
DELAY
1-16
D
E M
M U
U X
X
†
ODD/EVEN
NUMBER OF
TAPS
FIR A FORWARD PATH
DELAY
1-16
††
DELAY
1-16
††
DELAY
1-16
††
DELAY
1-16
††
DELAY
1-16
††
DELAY
1-16
††
SHFTEN
DELAY 3
†
DATA REVERSAL ENABLE
INA0-9
10
M
U
X
DELAY 3
DELAY 3
10
10
A
B
ALU
A
B
ALU
A
B
ALU
DELAY
1-16
††
DELAY
1-16
††
DELAY
1-16
††
DELAY
1-16
††
M
U
X
DELAY
1-16
††
DELAY
1-16
††
DELAY
1-16
††
FIR B REVERSE PATH
FIR B FORWARD PATH
5
INB0
INB1-9/
OUT0-8
FWRD
RVRS
CSEL0-4
CLK
ACCEN
MUX0-1
CIN0-9
A0-8
WR
9
†
ODD/EVEN
SYMMETRY
A
B
ALU
A
B
ALU
A
B
ALU
A
B
ALU
†
ODD/EVEN
SYMMETRY
A
B
ALU
DELAY 3
11
DELAY 3
REG
†
FIR B INPUT
SOURCE
REG
REG
REG
†
MODE SELECT
REG
REG
REG
REG
HSP43168
11
X
10
5
DELAY 4
21
REG
COEF
BANK
0
X
COEF
BANK
1
X
COEF
BANK
2
X
COEF
BANK
3
X
COEF
BANK
0
X
COEF
BANK
1
X
COEF
BANK
2
X
COEF
BANK
3
REG
REG
REG
REG
REG
REG
REG
FIR A
ACCUMULATOR
0
M
U
X
R
E
G
0
ADDER
22
OUTPUT
HOLDING
REGISTER
FIR B
ACCUMULATOR
M
U
X
R
E
G
ADDER
REG
DELAY 5
FIR CELL A
REG
OUTPUT
HOLDING
REGISTER
FIR CELL B
2
DELAY 6
10
9
CONTROL
†
MODE SELECT
†
ODD EVEN SYMMETRY
†
FIR A ODD/EVEN # TAPS
†
FIR B ODD/EVEN # TAPS
†
FIR B INPUT SOURCE
†
DATA REVERSAL ENABLE
†
ROUND ENABLE
†
DECIMATION FACTOR
MUX/
ADDER
28
DELAY 2
†
ROUND ENABLE
9
19
OUT9-27
FN2808.12
July 27, 2009
OEL
OEH
†
Processor control words
††
Decimation factor
FIGURE 1. DUAL FIR FILTER
