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HSP45256883

8-BIT, DSP-CORRELATOR, CPGA85

器件类别:半导体    嵌入式处理器和控制器   

厂商名称:Intersil ( Renesas )

厂商官网:http://www.intersil.com/cda/home/

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TM
HSP45256/883
Binary Correlator
The Intersil HSP45256/883 is a high-speed, 256 tap binary
correlator. It can be configured to perform one-dimensional
or two-dimensional correlations of selectable data precision
and length. Multiple HSP45256’s can be cascaded for
increased correlation length. Unused taps can be masked
out for reduced correlation length.
The correlation array consists of eight 32-tap stages. These
may be cascaded internally to compare 1, 2, 4 or 8-bit input
data with a 1-bit reference. Depending on the number of bits
in the input data, the length of the correlation can be up to
256, 128, 64, or 32 taps. The HSP45256 can also be
configured as two separate correlators with window sizes
from 4 by 32 to 1 by 128 each. The Mask Register can be
used to prevent any subset of the 256 bits from contributing
to the correlation score.
The9- output of the correlation array (correlation score)
feeds the weight and sum logic, which gives added flexibility
to the data format. In addition, an offset register is provided
so that a preprogrammed value can be added to the correla-
tion score. This result is then passed through a user pro-
grammable delay stage to the cascade summer. The delay
stage simplifies the cascading of multiple correlators by
compensating for the latency of previous correlators.
The Binary Correlator is configured by writing a set of control
registers via a standard microprocessor interface. To simplify
operation, both the Control and Reference Registers are
double buffered. This allows the user to load new mask and
reference data while the current correlation is in progress.
December 1999
Features
DUCT
UCT
E PRO UTE PROD L
ET
L
STIT
O B SO
ER SI
E SUB s 1-888-INT
SIBL
A POS Application intersil.com
FO R
entral
t a pp@
call C email: cen
or
Description
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Reconfigurable 256 Stage Binary Correlator
• 1-Bit Reference x 1, 2, 4, or 8-Bit Data
• Separate Control and Reference Interfaces
• Configurable for 1-D and 2-D Operation
• Double Buffered Mask and Reference
• Programmable Output Delay
• Cascadable
• Standard Microprocessor Interface
Applications
• Radar/Sonar
• Spread Spectrum Communications
• Pattern/Character Recognition
• Error Correction Coding
Ordering Information
PART NUMBER
HSP45256GM-20/883
HSP45256GM-25/883
TEMP.
RANGE (
o
C)
-55 to 125
-55 to 125
PACKAGE
85 Ld CPGA
85 Ld CPGA
PKG.
NO.
G85.A
G85.A
Block Diagram
DOUT0-7
DIN0-7
DREF0-7
WEIGHT
AND SUM
256 TAP
CORRELATION
ARRAY
MUX
AUXOUT0-8
DCONT0-7
CONTROL
A0-2
DELAY
CASCADE
SUMMER
CASOUT0-12
CASIN0-12
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
FN2997.4
1
HSP45256/883
Pinouts
1
A
2
3
4
85 PIN PGA
TOP VIEW
5
6
7
CAS
OUT
0
CAS
OUT
1
OEC
8
CAS
OUT
3
CAS
OUT
4
9
CAS
OUT
5
CAS
OUT
6
10
GND
CAS
OUT
7
CAS
OUT
9
GND
11
CAS
OUT
8
CAS
OUT
10
CAS
OUT
11
CAS
OUT
12
CASIN CASIN CASIN CASIN CASIN CASIN
2
4
5
7
10
11
GND
CASIN CASIN CASIN CASIN
1
3
6
9
CASIN INDEX
PIN
0
V
CC
CAS
OUT
2
B
C
CLK
CASIN CASIN
12
8
D
DIN7
E
F
DIN4
DREF
6
DIN0
DIN5
DIN3
DREF
7
DIN6
DIN2
DOUT0 DOUT1 DOUT2
DOUT DOUT
4
7
V
CC
DOUT
6
AUX
OUT
1
A1
DCONT DCONT
5
4
DCONT DCONT
OEA
6
2
AUX
OUT
6
AUX
OUT
8
GND
AUX
OUT
4
AUX
OUT
7
DOUT
3
DOUT
5
AUX
OUT
0
AUX
OUT
2
AUX
OUT
3
AUX
OUT
5
G
DIN1
H
DREF DREF
5
4
DREF DREF
3
1
DREF
2
DREF
0
V
CC
GND
R
LOAD
TXFR
C
LOAD
A2
J
K
A0
L
DCONT DCONT DCONT DCONT
7
1
3
0
85 PIN PGA
BOTTOM VIEW
L
DREF0
K
DREF2
V
CC
RLOAD
CLOAD
A0
DCONT
6
DCONT
2
OEA
AUXOUT
6
AUXOUT
4
AUXOUT
3
GND
TXFR
A2
DCONT
7
DCONT
1
DCONT
3
DCONT0
AUXOUT
8
AUXOUT
7
AUXOUT
5
J
DREF3
DREF1
A1
DCONT
5
DCONT
4
GND
AUXOUT
2
H
DREF5
G
DIN0
F
DREF6
E
DIN4
D
DIN7
V
CC
GND
CASOUT
12
DIN5
DIN6
DOUT0
DOUT1
DOUT2
DIN3
DIN2
DOUT4
DOUT7
DOUT3
DREF7
DIN1
V
CC
DOUT6
DOUT5
DREF4
AUXOUT
1
AUXOUT
0
C
CLK
CASIN0
INDEX
PIN
CASIN
8
CASIN
12
OEC
CASOUT
9
CASOUT
11
B
GND
CASIN1
CASIN3
CASIN6
CASIN
9
CASOUT
2
CASOUT
1
CASOUT CASOUT
4
6
CASOUT
7
CASOUT
10
A
CASIN
2
1
CASIN
4
2
CASIN
5
3
CASIN
7
4
CASIN
10
5
CASIN
11
6
CASOUT CASOUT
0
3
7
8
CASOUT
5
9
GND
10
CASOUT
8
11
9-2
HSP45256/883
Pin Description
SYMBOL
V
CC
GND
DIN0-7
PIN NUMBER
D2, G9, K2
A10, B1, D10,
J10, L2
D1, E1-E3, F2,
F3, G1, G3
E9-E11, F9-F11,
G10, G11
C1
A1-A6, B2-B5,
C2, C5, C6
A7-A9, A11,
B6-B11, C10,
C11, D11
I
TYPE
The +5V power supply pin.
Ground.
The DIN0-7 bus consists of eight single data input pins. The assignment of the active
pins is determined by the configuration. Data is loaded synchronous to the rising edge
of CLK. DIN0 is the LSB.
The DOUT0-7 bus is the data output of the correlation array. The format of the output
is dependent on the window configuration and bit weighting. DOUT0 is the LSB.
System Clock. Positive edge triggered.
CASIN0-12 allows multiple correlators to be cascaded by connecting CASOUT0-12 of
one correlator to CASIN0-12 of another. The CASIN bus is added internally to the
correlation score to form CASOUT. CASIN0 is the LSB.
CASOUT0-12 is the output correlation score. This value is the delayed sum of all the
256 taps of one chip and CASIN0-12. When the part is configured to act as two
independent correlators, CASOUT0-8 represents the correlation score for the first
correlator while the second correlation score is available on the AUXOUT0-8 bus. In
this configuration, the cascading feature is no longer an option. CASOUT0 is the LSB.
OEC is the output enable for CASOUT0-12. When OEC is high, the output is three-stat-
ed. Processing is not interrupted by this pin (active low).
TXFR is a synchronous clock enable signal that allows the loading of the reference and
mask inputs from the preload register to the correlation array. Data is transferred on the
rising edge of CLK while TXFR is low (active low).
DREF0-7 is an 8-bit wide data reference input. This is the input data bus used to load
the reference data. RLOAD going active initiates the loading of the reference registers.
This input bus is used to load the reference registers of the correlation array. The man-
ner in which the reference data is loaded is determined by the window configuration. If
the window configuration is 1 x 256, the reference bits are loaded one at a time over
DREF7. When the HSP45256 is configured as an 8 x 32 array, the data is loaded into
all stages in parallel. In this case, DREF7 is the reference data for the first stage and
DREF0 is the reference data for the eighth stage. The contents of the reference data
registers are not affected by changing the window configuration. DREF0 is the LSB.
RLOAD enables loading of the reference registers. Data on DREF0-7 is loaded into the
preload registers on the rising edge of RLOAD. This data is transferred into the corre-
lation array by TXFR (active low).
DCONT0-7 is the control data input, which is used to load the mask bit for each tap as
well as the configuration registers. The mask data is sequentially loaded into the eight
stages in the same manner as the reference data. DCONT0 is the LSB.
CLOAD enables the loading of the data on DCONT0-7. The destination of this data is
controlled by A0-2 (active low).
A0-2 is a 3-bit address that determines what function will be performed when CLOAD
is active. This address bus is set up with respect to the rising edge of the load signal,
CLOAD. A0 is the LSB.
AUXOUT0-8 is a 9-bit bus that provides either the data reference output or the 9-bit
correlation score of the second correlator, depending on the configuration. When the
user programs the chip to be two separate correlators, the score of the second correla-
tor is output on this bus. When the user has programmed the chip to be one correlator,
AUXOUT0-7 represents the reference data out, with the state of AUXOUT0-8
undefined. AUXOUT0 is the LSB.
The OEA signal is the output enable for the AUXOUT0-8 output. When OEA is high, the
output is disabled. Processing is not interrupted by this pin (active low).
Used for orienting pin in socket or printed circuit board. Must be left as a no connect in
circuit.
DESCRIPTION
DOUT0-7
CLK
CASIN0-12
O
I
I
CASOUT0-12
O
OEC
TXFR
C7
L3
I
I
DREF0-7
F1, G2, H1, H2,
J1, J2, K1, L1
I
RLOAD
K3
I
DCONT0-7
J6, J7, K6, K7,
L5-L8
K4
J5, K5, L4
I
CLOAD#
A0-2
I
I
AUXOUT0-8
H10, H11, J11,
K9-K11, L9-L11
O
OEA
Index Pin
K8
C3
I
9-3
HSP45256/883
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.5V to V
CC
+0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Reliability Information
θ
JC
Thermal Resistance (Typical, Note 1). . .
θ
JA
PGA Package . . . . . . . . . . . . . . . . . . . 36
o
C/W
10
o
C/W
Maximum Package Power Dissipation at 125
o
C
PGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.39W
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 175
o
C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300
o
C
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13,000 Gates
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Voltage Range (Typical) . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
GROUP A
SUB-
GROUPS
1, 2, 3
PARAMETER
Logical One Input
Voltage
Logical Zero Input
Voltage
Logical One Input
Voltage Clock
Logical Zero Input
Voltage Clock
Output HIGH Voltage
SYMBOL
V
IH
CONDITIONS
V
CC
= 5.5V
TEMPERATURE
(
o
C)
-55
T
A
125
-55
T
A
125
-55
T
A
125
-55
T
A
125
-55
T
A
125
-55
T
A
125
-55
T
A
125
-55
T
A
125
-55
T
A
125
MIN
2.2
MAX
-
UNITS
V
V
IL
V
CC
= 4.5V
1, 2, 3
-
0.8
V
V
IHC
V
CC
= 5.5V
1, 2, 3
3.0
-
V
V
ILC
V
CC
= 4.5V
1, 2, 3
-
0.8
V
V
OH
I
OH
= -400µA
V
CC
= 4.5V (Note 2)
I
OL
= +2.0mA
V
CC
= 4.5V (Note 2)
V
IN
= V
CC
or GND
V
CC
= 5.5V
V
IN
= V
CC
or GND
V
CC
= 5.5V
V
IN
= V
CC
or GND
V
CC
= 5.5V,
Outputs Open
f = 20 MHz, V
IN
= V
CC
or GND, V
CC
= 5.5V
(Note 3)
(Note 4)
1, 2, 3
2.6
-
V
Output LOW
Voltage
Input Leakage Current
V
OL
1, 2, 3
-
0.4
V
I
I
1, 2, 3
-10
+10
µA
µA
µA
Output Leakage Current
I
O
1, 2, 3
-10
+10
Standby Power Supply
Current
I
CCSB
1, 2, 3
-
500
Operating Power Supply
Current
I
CCOP
1, 2, 3
-55
T
A
125
-
140
mA
Functional Test
NOTES:
FT
7, 8
-55
T
A
125
-
-
-
2. Interchanging of force and sense conditions is permitted.
3. Operating Supply Current is proportional to frequency, typical rating is 7mA/MHz.
4. Tested as follows: f = 1MHz, V
IH
(clock inputs) = 3.4V, V
IH
(all other inputs) = 2.6V, V
IL
= 0.4V, V
OH
1.5V, and V
OL
1.5V.
9-4
HSP45256/883
TABLE 2. AC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested (Note 5)
GROUP A
SUB-
GROUPS
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
-25 (25.6MHz)
TEMPERATURE
(
o
C)
-55
T
A
125
-55
T
A
125
-55
T
A
125
-55
T
A
125
-55
T
A
125
-55
T
A
125
-55
T
A
125
-55
T
A
125
-55
T
A
125
-55
T
A
125
-55
T
A
125
-55
T
A
125
-55
T
A
125
-55
T
A
125
-55
T
A
125
-55
T
A
125
-55
T
A
125
-55
T
A
125
-55
T
A
125
-55
T
A
125
MIN
39
15
15
39
15
15
39
15
15
13
1
14
1
13
1
13
1
13
1
-
MAX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
20
-20 (20MHz)
MIN
50
20
20
50
20
20
50
20
20
15
1
15
1
15
1
15
1
15
1
-
MAX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
25
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PARAMETER
CLK Period
CLK High
CLK Low
CLOAD Cycle Time
CLOAD High
CLOAD Low
RLOAD Cycle Time
RLOAD High
RLOAD Low
Set-up Time; DIN to CLK
High
Hold Time; DIN to CLK
High
Set-up Time; DREF to
RLOAD High
Hold Time; DREF to
RLOAD High
DCONT Set up Time
DCONT Hold Time
Address Set up Time
Address Hold Time
TXFR Set up Time
TXFR Hold Time
CLK to Output Delay
DOUT, AUXOUT,
CASOUT
Output Enable Time
TXFR High to CLK Low
CLK Low to RLOAD,
CLOAD High
NOTES:
SYMBOL
t
CP
t
CH
t
CL
t
CLC
t
CLH
t
CLL
t
RLC
t
RLH
t
RLL
t
DS
t
DH
t
RS
t
RH
t
DCS
t
DCH
t
AS
t
AH
t
TS
t
TH
t
DO
(NOTE 5)
NOTES
t
OE
t
THCL
t
CLLH
Note 6
Note 7
Note 7
9, 10, 11
9, 10, 11
9, 10, 11
-55
T
A
125
-55
T
A
125
-55
T
A
125
-
3
1
20
-
-
-
4
1
20
-
-
ns
ns
ns
5. AC testing is performed as follows: V
CC
= 4.5V and 5.5V. Input levels (CLK input) 4.0V and 0V; input levels (all other inputs) 3.0V and
0V; Timing reference levels (CLK) 2.0V; all others 1.5V. Output load per test load circuit with C
L
= 40pF. Output transition is measured
at V
OH
1.5V and V
OL
1.5V.
6. Transition is measured at
±200mV
from steady state voltage, Output loading per test load circuit, C
L
= 40pF.
7. Applicable only when TXFR and RLOAD or CLOAD are active on the same cycle of CLK.
9-5
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参数对比
与HSP45256883相近的元器件有:HSP45256/883、HSP45256GM-20/883、HSP45256GM-25/883。描述及对比如下:
型号 HSP45256883 HSP45256/883 HSP45256GM-20/883 HSP45256GM-25/883
描述 8-BIT, DSP-CORRELATOR, CPGA85 8-BIT, DSP-CORRELATOR, CPGA85 8-BIT, DSP-CORRELATOR, CPGA85 8-BIT, DSP-CORRELATOR, CPGA85, CERAMIC, PGA-85
热门器件
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器件捷径:
E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ
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