HT16514
Dot Character VFD Controller & Driver
Features
·
Logic voltage: 2.7V~5.5V
·
High voltage: 60V (max.)
·
Provides a driving segment for cursor display
·
Display contents:
-
16 columns by 2 (1) rows + 32 (16) cursors
-
20 columns by 2 (1) rows + 40 (20) cursors
-
24 columns by 2 (1) rows + 48 (24) cursors
·
Supports display output (80-segment & 24-grid)
·
Parallel data input/output (switchable 4 bit or 8 bit) or
(48 units)
·
Alphanumeric and symbolic display through built-in
ROM
·
80´8-bit display RAM
·
On chip ROM (5´8 dot), in total 248 characters,
serial data input/output
·
Built-in oscillation circuit
·
144-pin LQFP package
plus 8 user-defined characters
·
Customized ROM acceptable
Applications
·
Consumer products panel function control
·
Industrial measuring instrument panel function
·
Other similar application panel function control
control
General Description
The HT16514 is a Vacuum Fluorescent Display, VFD
controller/driver with dot matrix VFD display. It consists
of 80 segment output lines and 24 grid output lines. It
can display up to 16C´2L, 20C´2L, 24C´2L.
The HT16514 has a character generator ROM which
stores up to 248´5´8 dot characters.
The HT16514 has serial/parallel interface. This VFD
controller/driver is ideal as an MCU peripheral device.
Ordering Information
Part Number
HT16514-001
HT16514-002
Package Information
144-pin plastic LQFP (Fine pitch) (20´20), standard ROM (ROM code: 001)
144-pin plastic LQFP (Fine pitch) (20´20), standard ROM (ROM code: 002)
Rev. 1.00
1
October 4, 2006
HT16514
Block Diagram
T E S T O
T E S T I
R L 2
R L 1
D L S
D S 1
D S 0
M P U
IM
C S
R S , S T
R , W
(W R )
S I, S O
D B 0 ~ D B 3
D B 4 ~ D B 7
4
8
4
8
In s tr u c tio n
R e g is te r ( IR )
In s tr u c tio n
D e c o rd e r
7
7
E (R D ), S C K
I/O
In te rfa c e
8
7
8
8
8
C r u s o r B lin k C ir c u it
7
A d d re s s
C o u n te r
8
D D R A M
( 8 0 x 8 B its )
7
7
T im in g
G e n e ra to r
4
2 4
2 4
2 4 - B it S h ift
R e g is te r
G 1
G r id D r iv e r
G 2 4
D a ta R e g is te r
(D R )
P a r a lle l to S e r ia l
D a ta C o n v e rte r
5
5
8 0 - B it O u tp u t
L a tc h & R e g is te r
8 0
C G R A M
( 8 x 5 x 8 B its )
C G R O M
( 2 4 8 x 5 x 8 B its )
S e g m e n t
D r iv e r
S 1
S 8 0
R E S E T
R E S E T
C ir c u it
O S C I
O S C O
X O U T
O S C
V D D
L G N D
V H
P G N D
S D O , S L K , C L , L E
Pin Assignment
S 3 5
S 3 6
S 3 7
S 3 8
S 3 9
S 4 0
S 4 1
S 4 2
S 4 3
S 4 4
S 4 5
S 4 6
S 4 7
S 4 8
S 4 9
S 5 0
S 5 1
S 5 2
S 5 3
S 5 4
S 5 5
S 5 6
S 5 7
S 5 8
S 5 9
S 6 0
S 6 1
S 6 2
S 6 3
S 6 4
S 6 5
S 6 6
S 6 7
S 6 8
S 6 9
S 7 0
S
S
S
S
S
S
S
S
S
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
S
N C
7 1
7 2
7 3
7 4
7 5
7 6
7 7
7 8
7 9
8 0
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
1 0
G 9
G 8
G 7
G 6
G 5
G 4
G 3
G 2
G 1
N C
1 0 8
1 0 9
7 3
7 2
H T 1 6 5 1 4
1 4 4 L Q F P -A
1 4 4
1
V H
3 6
3 7
N C
S 3
S 3
S 3
S 3
S 3
S 2
S 2
S 2
S 2
S 2
S 2
S 2
S 2
S 2
S 2
S 1
S 1
S 1
S 1
S 1
S 1
S 1
S 1
S 1
S 1
S 9
S 8
S 7
S 6
S 5
S 4
S 3
S 2
S 1
N C
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
V H
P G N
L G N
T E S
C L K
S D O
L E
C L
R L 2
R L 1
C S
M P U
IM
D B 7
D B 6
D B 5
D B 4
D B 3
D B 2
D B 1
D B 0
S I, S
E (R
R S ,
R , W
D S 0
D S 1
D L S
T E S
R E S
O S C
O S C
X O U
V D D
P G N
O
D ), S C K
S T
(W R )
T I
E T
I
D
D
T O
D
T
O
Rev. 1.00
2
October 4, 2006
HT16514
Pin Description
Pin Name
I/O
Description
Logic System (Microprocessor Interface)
When parallel mode is selected, this pin is utilized to select the register, either Instruction Reg-
ister or Data Register.
0: IR (Instruction Register)
1: DR (Data Register)
When serial mode is selected, this pin performs strobe input. Data can be set as input when
this signal goes 0.
During the next rising edge of this signal, command processing is performed.
When M68 parallel mode is selected (E), this pin is write enable. Writes data at the falling edge.
When i80 parallel mode is selected (RD), this pin is read enable. When this pin is
²Low²,
data is
output to the data Bus.
When Serial mode is selected, this pin is shift clock input, data will be written at the rising edge.
When this pin is
²Low²,
the device is active.
Connected to an external resistor to generate an oscillation frequency.
Oscillator signal output pin
When M68 parallel mode is selected (R, W), this pin is data mode select pin
(0: write, 1: read).
When i80 parallel mode is selected (WR), this pin is a write enable pin. Data will be written at
rising edge signal.
When serial mode is selected, connect this pin to
²Hi²
or
²Low².
Read or Write is chosen by in-
struction.
When serial mode is selected, this pin is used as I/O pin.
When parallel mode is selected, this pin needs to be connected to
²Hi²
or
²Low².
RS, ST
I
E (RD), SCK
I
CS
OSCI
OSCO
XOUT
I
I
O
O
R, W (WR)
I
SI, SO
I/O
DB0~DB7
When parallel mode is selected, these pins are used as I/O pins.
I/O Data are stored sequentially, the first bit which is sent to the HT16514 is MSB.
If 4 bits mode is selected, only DB4~DB7 are used.
I
I
Initialize all the internal register and commands.
All segments and digits are fixed PGND.
Set the duty ratio. Duty ratio will determine the number of grid.
The relationship between duty ratio and these pins is shown in Table 1-1.
Select interface mode (parallel mode or serial mode)
0: Serial mode
1: Parallel mode
In parallel mode, instruction will determine the length of word.
Select interface mode (i80 type CPU mode or M68 type CPU mode)
0: i80 type CPU mode
1: M68 type CPU mode
Select number of display line when power ON reset or resetting.
0: Select 1 line (N=0),
²N²
is display line select flag in Function set command.
1: Select 2 line (N=1)
Set segment outputs pin assignment. The selection table is listed as Table 1-2 & Table 1-7
0 or open: Normal operation mode
1: Test mode
For IC testing only, leave this pin open.
RESET
DS0, DS1
IM
I
MPU
I
DLS
RL1, RL2
TESTI
TESTO
I
I
I
O
Logic System ( To External Extension Driver)
SDO
SLK
O
O
Serial data output for extension digit driver.
Shift clock pulse for extension digit driver.
Active during rising edge
Rev. 1.00
3
October 4, 2006
HT16514
Pin Name
CL
LE
Output Pins
G1~G24
S1~S80
Power System
VDD
LGND
VH
PGND
¾
¾
¾
¾
Pins for logic circuit
LGND is ground pin for logic circuit
Power supply pins for VFD driver circuit
PGND is ground pin for VFD driver circuit
O
O
High-voltage output, grid output pins.
High-voltage output, segment output pins.
I/O
O
O
Description
Clear signal for extension digit driver, active low.
The digit data stored in the latch register of the extension driver are output when this signal is
²Hi²,
if this signal is
²Low²,
extension driver outputs are
²Low².
Latch enable signal for extension digit driver.
Table 1-1. Duty Ratio Setting
DS0
0
0
1
1
Note:
DS1
0
1
0
1
Duty Ratio
1/16 (# of grid = 16)
1/24 (# of grid = 24)
1/20 (# of grid = 20)
1/40 (# of grid = 40)*
* When setting to 1/40 duty mode, use the external extension grid driver.
Table 1-2. Segment Setting: 2 Line Display (N=1)
RL1
0
0
1
1
RL2
0
1
0
1
Table No.
Table 1-3
Table 1-4
Table 1-5
Table 1-6
Rev. 1.00
4
October 4, 2006
HT16514
Table 1-3. The Number Of Segment Pins 1
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Name
VH
PGND
VDD
XOUT
OSCO
OSCI
RESET
TESTI
DLS
DS1
DS0
R, W (WR)
RS, ST
E (RD), SCK
SI, SO
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
IM
MPU
CS
RL1
RL2
CL
LE
SDO
SLK
TESTO
LGND
PGND
VH
No.
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Name
NC
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
NC
No.
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
Name
S35
S36
S37
S38
S39
S40
S41
S42
S43
S44
S45
S46
S47
S48
S49
S50
S51
S52
S53
S54
S55
S56
S57
S58
S59
S60
S61
S62
S63
S64
S65
S66
S67
S68
S69
S70
No.
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
Name
NC
S71
S72
S73
S74
S75
S76
S77
S78
S79
S80
G24
G23
G22
G21
G20
G19
G18
G17
G16
G15
G14
G13
G12
G11
G10
G9
G8
G7
G6
G5
G4
G3
G2
G1
NC
Rev. 1.00
5
October 4, 2006
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