HT48E30
I/O Type 8-Bit MTP MCU With EEPROM
Technical Document
·
Tools Information
·
FAQs
·
Application Note
-
-
-
-
HA0086E
HA0087E
HA0088E
HA0089E
HT48E MCU Series - Using Assembly Language to Write to the 1K EEPROM Data Memory
HT48E MCU Series - Using C Language to Write to the 1K EEPROM Data Memory
HT48E MCU Series - Using Assembly Language to Write to the 2K EEPROM Data Memory
HT48E MCU Series - Using C Language to Write to the 2K EEPROM Data Memory
Features
·
Operating voltage:
·
Buzzer driving pair and PFD supported
·
HALT function and wake-up feature reduce power
f
SYS
=4MHz: 2.2V~5.5V
f
SYS
=8MHz: 3.3V~5.5V
·
Low voltage reset function
·
23 bidirectional I/O lines (max.)
·
1 interrupt input shared with an I/O line
·
8-bit programmable timer/event counter with overflow
consumption
·
4-level subroutine nesting
·
Up to 0.5ms instruction cycle with 8MHz system clock
at V
DD
=5V
·
Bit manipulation instruction
·
14-bit table read instruction
·
63 powerful instructions
·
10
6
erase/write cycles EEPROM data memory
·
EEPROM data retention > 10 years
·
All instructions in one or two machine cycles
·
In system programming (ISP)
·
24/28-pin SKDIP/SOP package
interrupt and 8-stage prescaler
·
On-chip crystal and RC oscillator
·
Watchdog Timer
·
1,000 erase/write cycles MTP program memory
·
2048´14 program memory ROM (MTP)
·
128´8 data memory EEPROM
·
96´8 data memory RAM
General Description
The HT48E30 is an 8-bit high performance, RISC archi-
tecture microcontroller device specifically designed for
multiple I/O control product applications.
The advantages of low power consumption, I/O flexibil-
ity, timer functions, oscillator options, HALT and
wake-up functions, watchdog timer, buzzer driver, as
well as low cost, enhance the versatility of these devices
to suit a wide range of application possibilities such as
industrial control, consumer products, subsystem con-
trollers, etc.
Rev. 1.50
1
October 31, 2006
HT48E30
Block Diagram
IN T /P G 0
In te rru p t
C ir c u it
S T A C K
4 L e v e ls
T M R 0
IN T C
T M R 0 C
P G 0
In s tr u c tio n
R e g is te r
M
U
X
W D T S
D A T A
M e m o ry
W D T P r e s c a le r
W D T
M
U
X
M
U
X
P r e s c a le r
T M R /P C 0
M
U
X
f
S
Y S
P ro g ra m
M e m o ry
P ro g ra m
C o u n te r
E N /D IS
f
S
Y S
/4
M P
W D T O S C
P A C
In s tr u c tio n
D e c o d e r
A L U
T im in g
G e n e ra to r
S h ifte r
M U X
P A
B Z /B Z
P B C
P G 1
P G 2
P B
P C C
O S C 2
O S
R E
V D
V S
C 1
S
D
S
A C C
P C
P O R T C
P O R T B
P B 0 ~ P B 7
P O R T A
P A 0 ~ P A 7
S T A T U S
P C 0 ~ P C 5
D a ta M e m o ry
E E P R O M
E E C R
P G C
P G
P O R T G
P G 0
Pin Assignment
P B 5
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
P B 4
P B 5
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
P B 4
P A 3
P A 2
P A 1
P A 0
P B 3
P B 2
P B 1 /B Z
P B 0 /B Z
V S S
P G 0 /IN T
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
P B 6
P B 7
P A 4
P A 5
P A 6
P A 7
O S C 2
O S C 1
V D D
R E S
P C 2
P C 0 /T M R
P A 3
P A 2
P A 1
P A 0
P B 3
P B 2
P B 1 /B Z
P B 0 /B Z
V S S
P G 0 /IN T
P C 0 /T M R
P C 1
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
P B 6
P B 7
P A 4
P A 5
P A 6
P A 7
O S C 2
O S C 1
V D D
R E S
P C 5
P C 4
P C 3
P C 2
H T 4 8 E 3 0
2 4 S K D IP -A /S O P -A
H T 4 8 E 3 0
2 8 S K D IP -A /S O P -A
Rev. 1.50
2
October 31, 2006
HT48E30
Pin Description
Pin Name
I/O
Options
Pull-high*
Wake-up
CMOS/Schmitt trigger
Input
Description
Bidirectional 8-bit input/output port. Each pin can be configured as a
wake-up input by options. Software instructions determine the CMOS
output or Schmitt trigger or CMOS input (depends on options) with
pull-high resistor (determined by 1-bit pull-high options).
Bidirectional 8-bit input/output port. Software instructions determine the
CMOS output or Schmitt trigger input with pull-high resistor (deter-
mined by pull-high options).
The PB0 and PB1 are pin-shared with the BZ and BZ, respectively.
Once the PB0 or PB1 is selected as buzzer driving outputs, the output
signals come from an internal PFD generator (shared with timer/event
counter).
Negative power supply, ground
Bidirectional I/O lines. Software instructions determine the CMOS out-
put or Schmitt trigger input with pull-high resistor (determined by 1-bit
pull-high options). This external interrupt input is pin-shared with PG0.
The external interrupt input is activated on a high to low transition.
Bidirectional I/O lines. Software instructions determine the CMOS out-
put or Schmitt trigger input with pull-high resistor (determined by 1-bit
pull-high options). The timer input are pin-shared with PC0.
Schmitt trigger reset input. Active low.
Positive power supply
OSC1and OSC2 are connected to an RC network or Crystal (deter-
mined by options) for the internal system clock. In the case of RC oper-
ation, OSC2 is the output terminal for 1/4 system clock.
PA0~PA7
I/O
PB0/BZ
PB1/BZ
PB2~PB7
I/O
Pull-high*
PB0 or BZ
PB1 or BZ
VSS
¾
¾
PG0/INT
I/O
Pull-high*
PC0/TMR
PC1~PC5
RES
VDD
OSC1
OSC2
Note:
I/O
I
¾
I
O
Pull-high*
¾
¾
Crystal or RC
²*²
The pull-high resistors of each I/O port (PA, PB, PC, PG) are controlled by a 1-bit option.
CMOS or Schmitt trigger option of port A is controlled by a 1-bit option.
Absolute Maximum Ratings
Supply Voltage ...........................V
SS
-0.3V
to V
SS
+6.0V
Input Voltage..............................V
SS
-0.3V
to V
DD
+0.3V
I
OL
Total ..............................................................150mA
Total Power Dissipation .....................................500mW
Note: These are stress ratings only. Stresses exceeding the range specified under
²Absolute
Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Storage Temperature ............................-50°C to 125°C
Operating Temperature...........................-40°C to 85°C
I
OH
Total............................................................-100mA
D.C. Characteristics
Symbol
Parameter
Test Conditions
V
DD
¾
¾
3V
Operating Current (Crystal OSC)
5V
I
DD2
3V
Operating Current (RC OSC)
5V
No load, f
SYS
=4MHz
Conditions
f
SYS
=4MHz
f
SYS
=8MHz
No load, f
SYS
=4MHz
Min.
2.2
3.3
¾
¾
¾
¾
Typ.
¾
¾
0.6
2
0.8
2.5
Max.
5.5
5.5
1.5
4
1.5
4
Ta=25°C
Unit
V
V
mA
mA
mA
mA
V
DD
Operating Voltage
I
DD1
Rev. 1.50
3
October 31, 2006
HT48E30
Symbol
I
DD3
Parameter
Operating Current
(Crystal OSC, RC OSC)
Standby Current (WDT Enabled)
5V
I
STB2
V
IL1
V
IH1
V
IL2
V
IH2
V
LVR
I
OL
3V
Standby Current (WDT Disabled)
5V
Input Low Voltage for I/O Ports
Input High Voltage for I/O Ports
Input Low Voltage (RES)
Input High Voltage (RES)
Low Voltage Reset Voltage
I/O Port Sink Current
5V
I
OH
3V
I/O Port Source Current
5V
R
PH
3V
Pull-high Resistance
5V
¾
¾
¾
¾
¾
3V
¾
¾
¾
¾
LVR enabled
V
OL
=0.1V
DD
V
OL
=0.1V
DD
V
OH
=0.9V
DD
V
OH
=0.9V
DD
¾
¾
No load*, system HALT
Test Conditions
V
DD
5V
3V
No load*, system HALT
Conditions
No load, f
SYS
=8MHz
Min.
¾
¾
¾
¾
¾
0
0.7V
DD
0
0.9V
DD
2.7
4
10
-2
-5
20
10
Typ.
Max.
Unit
4
¾
¾
¾
¾
¾
¾
¾
¾
3.0
8
20
-4
-10
60
30
8
5
10
1
2
0.3V
DD
V
DD
0.4V
DD
V
DD
3.3
¾
¾
¾
¾
100
50
mA
mA
mA
mA
mA
V
V
V
V
V
mA
mA
mA
mA
kW
kW
I
STB1
Note:
²*²
All tests are conducted with the I/O pins setup as outputs and set to a low value.
A.C. Characteristics
Symbol
Parameter
Test Conditions
V
DD
¾
¾
¾
¾
¾
¾
3V
Watchdog Oscillator Period
5V
t
WDT1
t
WDT2
t
RES
t
SST
t
INT
Watchdog Time-out Period
(WDT OSC)
Watchdog Time-out Period
(System Clock)
External Reset Low Pulse Width
System Start-up Timer Period
Interrupt Pulse Width
3V
Without WDT prescaler
5V
¾
¾
¾
¾
Without WDT prescaler
¾
Wake-up from HALT
¾
8
¾
1
¾
1
17
1024
¾
1024
¾
33
¾
¾
¾
¾
Conditions
2.2V~5.5V
3.3V~5.5V
2.2V~5.5V
3.3V~5.5V
2.2V~5.5V
3.3V~5.5V
¾
¾
Min.
400
400
400
400
0
0
45
32
11
Typ.
¾
¾
¾
¾
¾
¾
90
65
23
Max.
4000
8000
4000
8000
4000
8000
180
130
46
Ta=25°C
Unit
kHz
kHz
kHz
kHz
kHz
kHz
ms
ms
ms
ms
t
SYS
ms
t
SYS
ms
f
SYS1
System Clock (Crystal OSC)
f
SYS2
System Clock (RC OSC)
f
TIMER
Timer I/P Frequency (TMR)
t
WDTOSC
Rev. 1.50
4
October 31, 2006
HT48E30
Functional Description
Execution Flow
The HT48E30 system clock is derived from either a
crystal or an RC oscillator and is internally divided into
four non-overlapping clocks. One instruction cycle con-
sists of four system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while de-
coding and execution takes the next instruction cycle.
This pipelining scheme ensures that instructions are ef-
fectively executed in one cycle. If an instruction changes
the contents of the program counter, two cycles are re-
quired to complete the instruction.
Program Counter
-
PC
The program counter (PC) controls the sequence in
which the instructions stored in the program ROM are
executed and its contents specify a full range of pro-
gram memory.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
T 1
T 2
T 3
T 4
T 1
T 2
incremented by one. The program counter then points to
the memory word containing the next instruction code.
When executing a jump instruction, conditional skip ex-
ecution, loading into the PCL register, subroutine call or
return from subroutine, initial reset, internal interrupt,
external interrupt or return from interrupt, the PC manip-
ulates the program transfer by loading the address cor-
responding to each instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed with the next instruction.
The lower byte of the program counter (PCL) is a read-
able and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within the current program ROM page.
When a control transfer takes place, an additional
dummy cycle is required.
S y s te m
C lo c k
T 3
T 4
T 1
T 2
T 3
T 4
O S C 2 ( R C o n ly )
P C
P C
P C + 1
P C + 2
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Program Counter
*10
0
0
0
*9
0
0
0
*8
0
0
0
*7
0
0
0
*6
0
0
0
*5
0
0
0
*4
0
0
0
*3
0
0
1
*2
0
1
0
*1
0
0
0
*0
0
0
0
Mode
Initial Reset
External Interrupt
Timer/Event Counter Overflow
Skip
Loading PCL
Jump, Call Branch
Return from Subroutine
Program Counter+2
*10
#10
S10
*9
#9
S9
*8
#8
S8
@7
#7
S7
@6
#6
S6
@5
#5
S5
@4
#4
S4
@3
#3
S3
@2
#2
S2
@1
#1
S1
@0
#0
S0
Program Counter
Note: *10~*0: Program counter bits
#10~#0: Instruction code bits
S10~S0: Stack register bits
@7~@0: PCL bits
Rev. 1.50
5
October 31, 2006
嵌入式系统
