HUF75639S3R4851
TM
Data Sheet
April 2000
File Number
4854
56A, 115V, 0.025 Ohm, N-Channel
UltraFET Power MOSFET
This N-Channel power MOSFETs is manufactured using the
innovative UltraFET™ process. This advanced process
technology achieves the lowest possible on-resistance per
silicon area, resulting in outstanding performance. This
device is capable of withstanding high energy in the
avalanche mode and the diode exhibits very low reverse
recovery time and stored charge. It was designed for use in
applications where power efficiency is important, such as
switching regulators, switching converters, motor drivers,
relay drivers, low-voltage bus switches, and power
management in portable and battery-operated products.
Formerly developmental type TA75639.‘
Features
• 56A, 115V
• Simulation Models
- Temperature Compensated PSPICE
TM
and SABER
©
Electrical Models
- Spice and Saber Thermal Impedance Models
- www.Intersil.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
Ordering Information
PART NUMBER
HUF75639S3R4851
PACKAGE
TO-262AA
R4851
BRAND
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
NOTE: When ordering, use the entire part number.
Packaging
JEDEC TO-262AA
SOURCE
DRAIN
GATE
Symbol
D
G
S
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
HUF75639S3R4851
UNITS
V
V
V
A
115
115
±20
56
Figure 4
Figures 6, 14, 15
200
1.35
-55 to 175
300
260
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DSS
Drain to Gate Voltage (R
GS
= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Drain Current
Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
DM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
AS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
Derate Above 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
L
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
pkg
W
W/
o
C
o
C
o
C
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 150
o
C.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil and Design is a trademark of Intersil Corporation.
|
Copyright
©
Intersil Corporation 2000
PSPICE® is a registered trademark of MicroSim Corporation.
|
SABER™ is a trademark of Analogy, Inc.
UltraFET® is a registered trademark of Intersil Corporation.
HUF75639S3R4851
Electrical Specifications
PARAMETER
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
BV
DSS
I
DSS
I
D
= 250µA, V
GS
= 0V (Figure 11)
V
DS
= 95V, V
GS
= 0V
V
DS
= 90V, V
GS
= 0V, T
C
= 150
o
C
Gate to Source Leakage Current
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
Drain to Source On Resistance
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
SWITCHING SPECIFICATIONS
(V
GS
= 10V)
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Gate Charge at 10V
Threshold Gate Charge
Gate to Source Gate Charge
Reverse Transfer Capacitance
CAPACITANCE SPECIFICATIONS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
C
ISS
C
OSS
C
RSS
V
DS
= 25V, V
GS
= 0V,
f = 1MHz
(Figure 12)
-
-
-
2000
500
65
-
-
-
pF
pF
pF
Q
g(TOT)
Q
g(10)
Q
g(TH)
Q
gs
Q
gd
V
GS
= 0V to 20V
V
GS
= 0V to 10V
V
GS
= 0V to 2V
V
DD
= 50V,
I
D
≅
56A,
R
L
= 0.89Ω
I
g(REF)
= 1.0mA
(Figure 13)
-
-
-
-
-
110
57
3.7
9.8
24
130
75
4.5
-
-
nC
nC
nC
nC
nC
t
ON
t
d(ON)
t
r
t
d(OFF)
t
f
t
OFF
V
DD
= 50V, I
D
≅
56A,
R
L
= 0.89Ω, V
GS
=
10V,
R
GS
= 5.1Ω
-
-
-
-
-
-
-
15
60
20
25
-
110
-
-
-
-
70
ns
ns
ns
ns
ns
ns
R
θJC
R
θJA
(Figure 3)
TO-262
-
-
-
-
0.74
62
o
C/W
o
C/W
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
115
-
-
-
-
-
-
-
-
1
250
±100
V
µA
µA
nA
I
GSS
V
GS
=
±20V
V
GS(TH)
r
DS(ON)
V
GS
= V
DS
, I
D
= 250µA (Figure 10)
I
D
= 56A, V
GS
= 10V (Figure 9)
2
-
-
0.021
4
0.025
V
Ω
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
Reverse Recovered Charge
SYMBOL
V
SD
t
rr
Q
RR
I
SD
= 56A
I
SD
= 56A, dI
SD
/dt = 100A/µs
I
SD
= 56A, dI
SD
/dt = 100A/µs
TEST CONDITIONS
MIN
-
-
-
TYP
-
-
-
MAX
1.25
110
320
UNITS
V
ns
nC
2
HUF75639S3R4851
Typical Performance Curves
1.2
POWER DISSIPATION MULTIPLIER
1.0
0.8
0.6
0.4
0.2
0
0
25
50
75
100
125
150
175
T
C
, CASE TEMPERATURE (
o
C)
I
D
, DRAIN CURRENT (A)
60
50
40
30
20
10
0
25
50
75
100
125
150
175
T
C
, CASE TEMPERATURE (
o
C)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
1
Z
θJC
, NORMALIZED
THERMAL IMPEDANCE
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
P
DM
t
1
t
2
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
θJC
x R
θJC
+ T
C
10
-2
t, RECTANGULAR PULSE DURATION (s)
10
-1
10
0
10
1
0.1
SINGLE PULSE
0.01
10
-5
10
-4
10
-3
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
1000
T
C
= 25
o
C
I
DM
, PEAK CURRENT (A)
FOR TEMPERATURES
ABOVE 25
o
C DERATE PEAK
CURRENT AS FOLLOWS:
I = I
25
100
V
GS
= 10V
175 - T
C
150
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
10
-5
10
-4
10
-3
10
-2
t, PULSE WIDTH (s)
10
-1
10
0
10
1
FIGURE 4. PEAK CURRENT CAPABILITY
3
HUF75639S3R4851
Typical Performance Curves
1000
I
AS
, AVALANCHE CURRENT (A)
T
J
= MAX RATED
T
C
= 25
o
C
I
D
, DRAIN CURRENT (A)
(Continued)
300
If R = 0
t
AV
= (L)(I
AS
)/(1.3*RATED BV
DSS
- V
DD
)
If R
≠
0
t
AV
= (L/R)ln[(I
AS
*R)/(1.3*RATED BV
DSS
- V
DD
) +1]
100
STARTING T
J
= 25
ο
C
STARTING T
J
= 150
ο
C
100
100µs
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
DS(ON)
1
1
10
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
100
200
1ms
V
DSS(MAX)
= 115V
10ms
10
0.001
0.01
0.1
1
t
AV
, TIME IN AVALANCHE (ms)
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
100
V
GS
= 6V
I
D
, DRAIN CURRENT (A)
I
D
, DRAIN CURRENT (A)
80
V
GS
= 20V
V
GS
= 10V
V
GS
= 7V
100
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
DD
= 15V
175
o
C
80
60
60
40
V
GS
= 5V
20
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
T
C
= 25
o
C
0
1
2
3
4
5
6
7
40
20
25
o
C
0
0
1.5
3.0
4.5
6.0
7.5
V
GS
, GATE TO SOURCE VOLTAGE (V)
-55
o
C
0
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 8. TRANSFER CHARACTERISTICS
3.0
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
2.5 V
GS
= 10V, I
D
= 56A
2.0
1.5
1.0
0.5
0
-80
NORMALIZED GATE
1.2
V
GS
= V
DS
, I
D
= 250µA
THRESHOLD VOLTAGE
1.0
0.8
-40
0
40
80
120
160
200
0.6
-80
-40
0
40
80
120
160
200
T
J
, JUNCTION TEMPERATURE (
o
C)
T
J
, JUNCTION TEMPERATURE (
o
C)
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
4
HUF75639S3R4851
Typical Performance Curves
1.2
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
I
D
= 250µA
2500
C, CAPACITANCE (pF)
1.1
2000
C
ISS
1500
1000
C
OSS
500
C
RSS
0.9
-80
0
-40
0
40
80
120
160
200
0
10
20
30
40
50
60
T
J
, JUNCTION TEMPERATURE (
o
C)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
(Continued)
3000
V
GS
= 0V, f = 1MHz
C
ISS
= C
GS
+ C
GD
C
RSS
= C
GD
C
OSS
≈
C
DS
+ C
GD
1.0
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
10
V
GS
, GATE TO SOURCE VOLTAGE (V)
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
I
D
= 56A
I
D
= 37A
I
D
= 18A
30
40
50
60
2
V
DD
= 50V
0
0
10
20
Qg, GATE CHARGE (nC)
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
V
DS
BV
DSS
L
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
V
GS
DUT
t
P
R
G
I
AS
V
DD
t
P
V
DS
V
DD
+
-
0V
I
AS
0.01Ω
0
t
AV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
5
