HV100/HV101
3-Pin Hotswap, Inrush Current Limiter Controllers
(Negative Supply Rail)
Features
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33% Smaller than SOT-232
Pass Element is Only External Part
No Sense Resistor required
Auto-adapt* to Pass Element
Short Circuit Protection*
UV & POR Supervisory Circuits
2.5s Auto Retry
±10V to ±72V Input Voltage Range
0.6mA Typical Operating Supply Current
Built in Clamp for AC Path Turn On Glitch
General Description
The HV100 and the HV101 are 3-pin hotswap controllers
available in the SOT-223 package, which require no external
components other than a pass element. The HV100 and the
HV101 contain many of the features found in hotswap control-
lers with 8 pins or more, and which generally require many
external components. These features include undervoltage (UV)
detection circuits, power on reset (POR) supervisory circuits,
inrush current limiting, short circuit protection, and auto-retry.
In addition, the HV100 and the HV101 use a patent pending
mechanism to sample and adapt to any pass element, resulting
in consistent hotswap profiles without any programming.
The only difference between the HV100 and the HV101 is the
internally set undervoltage (UV) threshold.
*Patents Pending
Applications
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-48V Central Office Switching (line cards)
+48V Server Networks
+48V Storage Area Networks
+48V Peripherals, Routers, Switches
+24V Cellular and Fixed Wireless (bay stations,
line cards)
+24V Industrial Systems
+24V UPS Systems
-48V PBX & ADSL Systems (line cards)
Distributed Power Systems
Powered Ethernet for VoIP
Typical Application Circuit and Waveforms
GND
V
PP
400F
GATE
DC/DC
Converter
+5V
COM
HV100
V
NN
-48V
IRF530
HV100/HV101
Ordering Information
UV Options
34V
14V
Package Options
3-Pin SOT-223
HV100K5
HV101K5
HV100K5-G
HV101K5-G
Pin Configuration
-G indicates package is RoHS compliant (‘Green’)
1
VPP
2
VNN
(Top View)
3
GATE
3-Lead SOT-223
Absolute Maximum Ratings
Parameter
V
PP
Input Voltage
Operating Ambient Temperature Range
Operating Junction Temperature Range
Storage Temperature Range
Value
-0.3V - 75.0V
-40 C to +85 C
-40 C to +125 C
-65
o
C to +150
o
C
GATE
o
o
o
o
Pin Description
Pin
V
PP
V
NN
Function
Positive voltage power supply to the circuit.
Negative voltage power supply to the circuit.
Gate driver output for the external n-Channel
MOSFET
Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions is not implied. Continuous operation
of the device at the absolute rating level may affect device reliability. All voltages are
referenced to device ground.
DC Electrical Characteristics
(V
Sym.
Parameter
Supply (Referenced to V
PP
pin)
V
NN
I
NN
Supply Voltage
Supply Current
H
= V
DD
= 12V, V
L
= V
SS
= GND = 0V, V
OE
= 3.3V, T
J
= 25°C)
Min.
Typ.
Max.
Units
Conditions
-72
-
-
0.6
UV
1.0
V
mA
---
V
NN
= -48.0V
UV Control (Referenced to V
NN
pin)
V
UVL
V
UVH
UV Threashold (High to Low)
30
12.3
-
-
34
14
3
1
38
15.7
-
-
V
V
V
V
HV100
HV101
HV100
HV101
UV Hysteresis
Gate Drive Output (Referenced to V
NN
pin)
V
GATE
SR
GATE
I
GATEDOWN
I
PULLUP
Maximum Gate Drive Voltage
Initial Slew Rate
Gate Drive Pull-Down Current
(Sinking)
Post Hot Swap Pull-Up Current
10
1.5
8
6
12
-
16
11
14
3.75
-
-
V
V/ms
mA
μA
---
C
GATE
= 1nF
V
GATE
= 1.0V; V
PP
= 11.5V
V
GATE
= 6.0V
2
HV100/HV101
DC Electrical Characteristics
(cont.)
Sym
Parameter
Min
Typ
Max
Units
Conditions
Timing Control (Referenced to V
NN
pin)
t
POR
t
ARD
Insertion POR Delay
Auto Restart Delay
1.5
1.25
3.5
2.5
5.5
3.75
ms
s
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Example Electrical Results (Using IRF530)
I
LIM
I
LIM
I
LIM
I
SHORT
t
SHORT
Δ
GATE
t
HS
Max Inrush Current During
Hotswap
Max Inrush Current During
Hotswap
Max Inrush Current During
Hotswap
Max Current Into a Short
Shorted Load Detect Time
Initial Rate of Rise of Gate
Hot Swap Period to Full Gate
Value
-
-
-
-
-
-
-
1.4
2.5
3.1
4.0
1.0
2.5
12.5
-
-
-
-
-
-
A
A
A
A
ms
V/ms
ms
IRF530 external MOSFET, C
LOAD
=
100μF
IRF530 external MOSFET, C
LOAD
=
200μF
IRF530 external MOSFET, C
LOAD
=
300μF
IRF530 external MOSFET, R
LOAD
=
<<1.5
IRF530 external MOSFET, R
LOAD
=
<<1.5
IRF530 external MOSFET, any C
LOAD
IRF530 external MOSFET, any C
LOAD
Functional Block Diagram
V
PP
Regulator
UVLO
Reference
Generator
UV
POR
Timer
Logic
Restart
Timer
GATE
V
NN
3
HV100/HV101
Functional Description
Insertion into Hot Backplanes
Telecom, data network and some computer applications
require the ability to insert and remove circuit cards from
systems without powering down the entire system. Since all
circuit cards have some filter capacitance on the power rails,
which is especially true in circuit cards or network terminal
equipment utilizing distributed power systems, the insertion
can result in high inrush currents that can cause damage to
connector and circuit cards and may result in unacceptable
disturbances on the system backplane power rails.
The HV100 and HV101 are designed to facilitate the insertion
and removal of these circuit cards or connection of terminal
equipment by eliminating these inrush currents and powering
up these circuits in a controlled manner after full connector
insertion has been achieved. The HV100 and HV101 are
intended to provide this control function on the negative sup-
ply rail.
After completion of a full POR period, the MOSFET gate auto-
adapt operation begins. A reference current source is turned
on which begins to charge an internal capacitor generating
a ramp voltage which rises at a slew rate of 2.5 V/ms. This
reference slew rate is used by a closed loop system to gen-
erate a GATE output current to drive the gate of the external
N-channel MOSFET with a slew rate that matches the refer-
ence slew rate. Before the gate crosses a reference voltage,
which is well below the V
TH
of industry standard MOSFETs,
the pull-up current value is stored and the auto-adapt loop
is opened. This stored pull-up current value is used to drive
the gate during the remainder of the hot swap period. The
result is a normalization with C
ISS
, which for most MOSFETs
scales with C
RSS
.
The MOSFET gate is charged with a current source until it
reaches its turn on threshold and starts to charge the load
capacitor. At this point the onset of the Miller Effect causes
the effective capacitance looking into the gate to rise, and
the current source charging the gate will have little effect on
the gate voltage. The gate voltage remains essentially con-
stant until the output capacitor is fully charged. At this point
the voltage on the gate of the MOSFET continues to rise to
a voltage level that guarantees full turn on of the MOSFET.
It will remain in the full on state until an input under voltage
condition is detected.
If the circuit attempts turn on into a shorted load, then the
Miller Effect will not occur. The gate voltage will continue to rise
essentially at the same rate as the reference ramp indicating
that a short circuit exists. This is detected by the control circuit
and results in turning off the MOSFET initiating a 2.5 second
delay, after which a normal restart is attempted.
If at any time during the start up cycle or thereafter, the input
voltage falls below the UV threshold the GATE output will
be pulled down to V
NN
, turning off the N-channel MOSFET
and all internal circuitry is reset. A normal restart sequence
will be initiated once the input voltage rises above the UVLO
threshold plus hysteresis.
Description of Operation
On initial power application the high input voltage internal
regulator seeks to provide a regulated supply for the internal
circuitry. Until the proper internal voltage is achieved all circuits
are held reset by the internal UVLO and the gate to source
voltage of the external N-channel MOSFET is held off. Once
the internal regulator voltage exceeds the UVLO threshold,
the input undervoltage detection circuit (UV) senses the input
voltage to confirm that it is above the internally programmed
threshold. If at any time the input voltage falls below the UV
threshold, all internal circuitry is reset and the GATE output
is pulled down to V
NN
. UVLO detection works in conjunction
with a power on reset (POR) timer of approximately 3.5ms to
overcome contact bounce. Once the UVLO is satisfied, the
gate is held to V
NN
until a POR timer expires. Should the UV
monitor toggle before the POR timer expires, the POR timer
will be reset. This process will be repeated each time UVLO
is satisfied until a full POR period has been achieved.
4
HV100/HV101
Application Information
Turn On Clamp
Hotswap controllers using a MOSFET as the pass element all
include a capacitor divider from V
PP
to V
NN
through C
LOAD
, C
RSS
and C
GS
. In most competitive solutions a large external capacitor
is added to the gate of the pass element to limit the voltage on
the gate resulting from this divider. In those instances, if a gate
capacitor is not used the internal circuitry is not available to
hold off the gate, and therefore a fast rising voltage input will
cause the pass element to turn on for a moment. This allows
current spikes to pass through the MOSFET.
The HV100 and HV101 include a built-in clamp to ensure
that this spurious current glitch does not occur. The built-in
clamp will work for the time constants of most mechanical
connectors. There may be applications, however, that have
rise times that are much less than 1µs (100’s of ns). In these
instances it may be necessary to add a capacitor from the
MOSFET gate to source to clamp the gate and suppress
this current spike. In these cases the current spike generally
contains very little energy and does not cause damage even
if a capacitor is not used at the gate.
Short Circuit Protection
The HV100 and HV101 provide short circuit protection by shut-
ting down if the Miller Effect associated with hotswap does not
occur. Specifically, if the output is shorted then the gate will
rise without exhibiting a “flat response”. Due to the fact that we
have normalized the hotswap period for any pass element, a
timer can be used to detect if the gate voltage rises above a
threshold within that time, indicating that a short exists. The
diagram below shows a typical turn on sequence with the load
shorted, resulting in a peak current of 4A.
Auto-adapt Operation
The HV100 and HV101 auto-adapt mechanism provides an
important function. It normalizes the hotswap period regardless
of pass element or load capacitor for consistent hotswap results.
By doing this it allows the novel short circuit mechanism to
work because the mechanism requires a known time base.
The maximum current that may occur during this period can
be controlled by adding a resistor in series with the source of
the MOSFET. The lower graph shows the same circuit with
a 100mΩ resistor inserted between source and V
NN
. In this
case the maximum current is 25% smaller.
The above diagram illustrates the effectiveness of the auto-
adapt mechanism. In this example three MOSFETs with dif-
ferent C
ISS
and R
DSON
values are used. The top waveform is
the hotswap current, while the bottom waveform is the gate
voltage. As can be seen, the hotswap period is normalized,
the initial slope of the gate voltage is approximately 2.5V/ms
regardless of the MOSFET, and the total hotswap period and
peak currents are a function of a MOSFET type dependent
constant multiplied by C
LOAD
.
Typically if MOSFETs of the same type are used, the hotswap
results will be extremely consistent. If different types are used
they will usually exhibit minimal variation.
5
For most applications and pass elements, the HV100 and
HV101 provides adequate limiting of the maximum current to
prevent damage without the need for any external components.
The 2.5s delay of the auto-retry circuit provides time for the
pass element to cool between attempts.
