1 of 8 Decoded 8-Channel High Voltage Analog Switch
Ordering Information
Package Options
V
PP
+80V
V
NN
-80V
V
SIG
130V P-P
20-pin Plastic
DIP
HV1516P
Die
HV1516X
Features
s
HVCMOS
®
Technology
s
Up to 130V peak to peak switching capability
s
Output on-resistance typically 40 ohms
s
Low parasitic capacitances
s
DC to 10MHz analog signal frequency
s
-45dB typical output off isolation at 5MHz
s
CMOS logic circuitry for low power
and excellent noise immunity
s
On-chip decode, latch and chip select logic circuitry
General Description
Not recommended for new designs. Please use HV202 or
HV207 instead.
This device is an 8-channel high-voltage integrated circuit (HVIC),
configured as a 1 of 8 decode function, intended for use in
applications requiring high voltage switching controlled by low
voltage signals; e.g., ultrasound imaging and printers. On-chip
latches are provided for the decoded data. Using HVCMOS
technology, this HVIC combines high voltage bilateral DMOS
switches and low power CMOS logic to provide efficient control of
high voltage analog signals.
Pin Configuration
13
Y4
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
Y2
Y1
Y0
Y3
A
B
C
CL
LE
Absolute Maximum Ratings*
V
DD
logic power supply voltage
V
PP
- V
NN
supply voltage
V
PP
positive high voltage supply
V
NN
negative high voltage supply
Logic input voltages
Analog signal range
Peak analog signal current/channel
Storage temperature
Power dissipation
-0.5V to +18V
174V
-0.5V to +90V
+0.5V to -90V
-0.5 to V
DD
+0.3V
V
NN
to V
PP
1.5A
-65°C to +150°C
1.2W
Y6
YC
Y7
Y5
CS
1
V
NN
GND
CS
2
V
PP
top view
* Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not implied.
Continuous operation of the device at the absolute rating level may affect
device reliability.
20-pin DIP
13-1
HV1516
Electrical Characteristics
(over operating conditions, V
PP
= +80V, V
NN
= -80V, and V
DD
= 15V unless otherwise noted)
DC Characteristics
Characteristics
Switch (ON) Resistance
Switch (ON) Resistance
Switch (ON) Resistance
Switch (ON) Resistance
Switch (ON) Resistance
Matching x and y (0-3)
Switch Off Leakage
Per Switch
DC Offset Switch Off
DC Offset Switch On
Pole to Pole
Switch Capacitance
Logic Input Capacitance
Pos. HV Supply Current
Neg. HV Supply Current
Pos. HV Supply Current
Neg. HV Supply Current
Pos. HV Supply Current
Neg. HV Supply Current
Switch Output
Peak Current
Logic Supply
Average Current
Logic Supply
Quiescent Current
I
DD
I
DDQ
C
SW
C
IN
I
PPQ
I
NNQ
I
PPQ
I
NNQ
I
PPQ
I
NNQ
200
-200
Sym
R
ONS
R
ONS
R
ONS
R
ONS
∆R
ONS
I
SOL
0
°
C
min max
50
35
55
40
30
50
500
500
10
min
+25
°
C
typ
40
25
45
25
10
0.5
100
100
4.5
3.5
50
-50
0.8
-0.8
0.6
-0.6
1.5
4.0
10
500
200
-200
1.6
-1.6
1.2
-1.2
200
-200
max
50
35
55
40
30
50
500
500
10
+70
°
C
min
max
60
45
65
50
30
150
500
500
10
Units
ohms
ohms
ohms
ohms
%
µA
mV
mV
pF
pF
µA
µA
mA
mA
mA
mA
A
mA
µA
1 SW ON, I
SW
= 5mA,
V
SIG
= 0V
V
PP
= +50V, V
NN
= -50V
1 SW ON, I
SW
= 5mA
V
SIG
≤
0.1% Duty Cycle,
f = 10KHz
Input Freq. = 3MHz
ALL SWS OFF
Test Conditions
I
SW
= 5mA, V
SIG
= 0V
I
SW
= 200mA, V
SIG
= 0V
V
PP
= +50V, V
NN
= -50V,
I
SW
= 5mA, V
SIG
= 0V
V
PP
= +50V, V
NN
= -50V,
I
SW
= 200mA, V
SIG
= 0V
V
PP
= +50V, V
NN
= -50V,
I
SW
= 5mA, V
SIG
= 0V
V
SIG
= V
PP
-10V thru 10KΩ
with 8 SWS in parallel
R
L
= 100KΩ
R
L
= 100KΩ
DC Bias = 40V
f = 1MHz
AC Characteristics
Characteristics
Data Hold Time After LE Rises
Set Up Time Before LE Rises
Time Width of LE
Time Width of CL
Turn On Time
Turn Off Time
Off Isolation
Switch Crosstalk
Sym
min
t
HD
t
SD
t
WLE
t
WCL
t
ON
t
OFF
KO
K
CR
5.0
10
-35
0
°
C
max
min
5.0
260
300
150
2.5
5.0
-45
-45
5.0
10
5.0
10
+25
°
C
typ
max
+70
°
C
min
max
ns
ns
ns
ns
µs
µs
dB
dB
R
L
= 10KΩ
R
L
= 10KΩ
Signal Freq. = 5MHz
Signal Freq. = 5MHz
Units
Test Conditions
13-2
HV1516
Operating Conditions
Symbol
V
DD
V
PP
V
NN
V
IH
V
IL
V
SIG
T
A
Parameter
Logic power supply voltage
1
Positive high voltage supply
1
Negative high voltage supply
1
High level input voltage
Low-level input voltage
Analog signal voltage peak to peak
2
Operating free air-temperature
Value
+10.0V to +15.5V
+50V to +80V
-50V to -80V
V
DD
-2V to V
DD
0 to 2.0V
V
NN
+15V to V
PP
-15V
0° to 70°C
Note:
1. Power up/down sequence is arbitrary except GND must be powered-up first and powered-down last.
2. V
SIG
must be V
NN
≤
V
SIG
≤
V
PP
or floating during power up/down transition.
Test Circuits
V
PP
-15V
I
SOL
V
PP
-15V
V
IN
= 10 V
P-P
@5MHz
V
OUT
50Ω
NC
R
L
V
OUT
10KΩ
V
NN
+15V
50Ω
+80V
-80V
V
PP
V
NN
V
DD
GND
15V
+80V
-80V
V
PP
V
NN
V
DD
GND
15V
+80V
-80V
V
PP
V
NN
V
DD
GND
15V
K
CR
= 20Log
V
OUT
V
IN
Switch OFF Leakage
Crosstalk
T
ON
/T
OFF
13
V
IN
= 10 V
P-P
@5MHz
V
OUT
V
OUT
R
L
100KΩ
R
L
+80V
-80V
V
PP
V
NN
V
DD
GND
15V
+80V
-80V
V
PP
V
NN
V
DD
GND
15V
K
O
= 20Log
V
OUT
V
IN
OFF Isolation
DC Offset ON/OFF
13-3
HV1516
Logic Timing Waveforms
LOGIC
INPUT
(TYP)
50%
50%
50%
tOFF
tSD
LE
50%
tWLE
tON
VOUT
(TYP)
OFF
ON
10%
tON
tOFF
CL
50%
tWCL
tON
50%
10%
tOFF
90%
50%
tHD
50%
Logic Diagram
LATCHES
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
LEVEL
SHIFTERS
OUTPUT
SWITCHES
Y
C
Y
0
A
B
Y
1
C
Y
2
CS
1
1:8
DECODER
Y
3
CS
2
Y
4
Y
5
Y
6
Y
7
V
NN
V
PP
V
DD
LE
CL
13-4
HV1516
Truth Table
C
L
L
L
L
H
H
H
H
X
X
X
X
B
L
L
H
H
L
L
H
H
X
X
X
X
A
L
H
L
H
L
H
L
H
X
X
X
X
CS
1
L
L
L
L
L
L
L
L
H
X
X
X
CS
2
L
L
L
L
L
L
L
L
X
H
X
X
LE
L
L
L
L
L
L
L
L
L
L
X
H
CL
L
L
L
L
L
L
L
L
L
L
H
L
ALL OUTPUTS OFF
ALL OUTPUTS OFF
ALL OUTPUTS OFF
HOLDS PREVIOUS STATE
Y0
ON
ON
ON
ON
ON
ON
ON
ON
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Notes:
1. Address data at A, B, C cause one of the eight switches to be selected for connection to the common bus Y
C
.
2. The clear input CL overrides all other inputs.
3. Since the latch follows the decoder, only the CL input matters when LE is H.
4. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low, the decoded selection address information flows through the latch.
