HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Document Title
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash Memory
Revision History
Revision
No.
0.0
1) Add Errata
tCLS
Specification
Relaxed value
0
5
Case
Specification
Read(all)
Except for
0.1
Relaxed value ID Read
ID Read
2) Add note.4(table14)
3) Add application note(Power on/off Sequence & Auto sleep mode)
- Texts & figures are added.
4) Change AC parameters
Case
Before
After
x8, x16
x8
x16
tDH
10
10
15
tCLH tWP tALS tALH
10
15
tRC
50
50
60
25
45
0
5
10
15
tDS
20
25
tWC
50
70
tR
25us
27us
History
Initial Draft.
Draft Date
Nov. 19. 2004
Remark
Preliminary
tRP tREH tREA
20
20
25
20
20
30
30
30
30
Jan. 20. 2005
Preliminary
1) Change AC parameters
case
Before
0.2
Afer
x8
x16
x8, x16
tDH
10
15
15
Mar. 03. 2005 Preliminary
2) Add tADL(=100ns) parameters
3) Add Muliti Die Concurrent Operations and Extended Read Status
- Texts and table are added.
4) Edit Table.8
5) Change FBGA Package Dimension
Rev 0.7 / Nov. 2005
1
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Revision History
Revision
No.
1) Change Errata
- Errata values (tWP & tWC) are changed
0.3
Before
After
tCLS
5
5
tCLH
15
15
tWP
45
40
tALS
5
5
tALH
15
15
tDS
25
25
tWC
70
60
tR
25us
27us
Apr. 01. 2005
Preliminary
-Continued-
History
Draft Date
Remark
1) Correct AC Timing Characristics Table
- Errata value is eddited.
- tADL(max) is changed to tADL(min)
2) Chage Errata
- tREA is deleted from the Errata
tRC tRP tREH
Case
0.4
before
after
Except for
ID Read
ID Read
50
60
20
25
20
30
30
Apr. 06. 2005
Preliminary
25
Read (all) 60
3) Correct Operating Current(Typ.)
- before : 10mA -> after : 15mA(3.3V)
- before : 8mA -> after : 10mA(1.8V)
1) Correct the test Conditions (DC Characteristics table)
Test Conditions (
I
CC1)
Before
After
Test Conditions (
I
LI,
I
LO
)
VIN=VOUT=0 to 3.6V
VIN=VOUT=0 to Vcc (max)
t
RC
=50ns, CE#=
V
IL
,
I
OUT
=0mA
t
RC
(1.8V=60ns,3.3V=50ns)
CE#=
V
IL
, I
OUT
=0mA
0.5
Aug. 05. 2005
Preliminary
2) Change AC Conditions table
3) Add tWW parameter ( tWW = 100ns, min)
- Texts & Figures are added.
- tWW is added in AC timing characteristics table.
4) Edit System Interface Using CE don’t care Figures.
5) Correct Address Cycle Map.
Rev 0.7 / Nov. 2005
2
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
Revision History
Revision
No.
History
1) Change 2Gb Package Type.
- FBGA package is deleted.
- WSOP package is changed to USOP package.
- Figure & dimension are changed.
2) Correct PKG dimension (TSOP, USOP PKG)
CP
Before
After
0.6
0.050
0.100
Oct. 19. 2005
-Continued-
Draft Date
Remark
3) Add tRBSY (Table 12)
- tRBSY (Dummy Busy Time for Cache Read)
- tRBSY is 5us (typ.)
4) Delete Errata
5) Change AC Characteristics
tRC
Before
After
60
60
50
tRP
25
40
25
tREH
30
30
20
1) Change Ac Characteristics
tRC
tRP
40
25
25
25
tREH
30
20
30
20
0.7
Before
Read ID
Data Read
Read ID
Data Read
60
50
60
50
Nov. 04. 2005
After
Rev 0.7 / Nov. 2005
3
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
FEATURES SUMMARY
HIGH DENSITY NAND FLASH MEMORIES
- Cost effective solutions for mass storage applications
NAND INTERFACE
- x8 or x16 bus width.
- Multiplexed Address/ Data
- Pinout compatibility for all densities
FAST BLOCK ERASE
- Block erase time: 2ms (Typ.)
STATUS REGISTER
ELECTRONIC SIGNATURE
- Manufacturer Code
- Device Code
SUPPLY VOLTAGE
- 3.3V device: VCC = 2.7 to 3.6V
: HY27UGXX2G2M
CHIP ENABLE DON'T CARE OPTION
- Simple interface with microcontroller
AUTOMATIC PAGE 0 READ AT POWER-UP OPTION
- Boot from NAND support
- Automatic Memory Download
SERIAL NUMBER OPTION
HARDWARE DATA PROTECTION
- Program/Erase locked during Power transitions
DATA INTEGRITY
- 100,000 Program/Erase cycles
- 10 years Data Retention
PACKAGE
- HY27(U/S)G(08/16)2G2M-T(P)
: 48-Pin TSOP1 (12 x 20 x 1.2 mm)
- HY27(U/S)G(08/16)2G2M-T (Lead)
- HY27(U/S)G(08/16)2G2M-TP (Lead Free)
- HY27(U/S)G(08/16)2G2M-S(P)
: 48-Pin USOP1 (12 x 17 x 0.65 mm)
- HY27(U/S)G(08/16)2G2M-S (Lead)
- HY27(U/S)G(08/16)2G2M-SP (Lead Free)
- 1.8V device: VCC = 1.7 to 1.95V : HY27SGXX2G2M
Memory Cell Array
= (2K+ 64) Bytes x 64 Pages x 2,048 Blocks
= (1K+32) Words x 64 pages x 2,048 Blocks
PAGE SIZE
- x8 device : (2K + 64 spare) Bytes
: HY27(U/S)G082G2M
- x16 device: (1K + 32 spare) Words
: HY27(U/S)G162G2M
BLOCK SIZE
- x8 device: (128K + 4K spare) Bytes
- x16 device: (64K + 2K spare) Words
PAGE READ / PROGRAM
- Random access: 27us (max.)
- Sequential access: 60ns (min.)
- Page program time: 300us (typ.)
COPY BACK PROGRAM MODE
- Fast page copy without external buffering
CACHE PROGRAM MODE
- Internal Cache Register to improve the program
throughput
Rev 0.7 / Nov. 2005
4
HY27UG(08/16)2G2M Series
HY27SG(08/16)2G2M Series
2Gbit (256Mx8bit / 128Mx16bit) NAND Flash
1. SUMMARY DESCRIPTION
The HYNIX HY27(U/S)G(08/16)2G2M series is a 256Mx8bit with spare 8Mx8 bit capacity. The device is offered in 1.8V
Vcc Power Supply and in 3.3V Vcc Power Supply.
Its NAND cell provides the most cost-effective solution for the solid state mass storage market.
The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old
data is erased.
The device contains 2048 blocks, composed by 64 pages consisting in two NAND structures of 32 series connected
Flash cells.
A program operation allows to write the 2112-byte page in typical 300us and an erase operation can be performed in
typical 2ms on a 128K-byte(X8 device) block.
Data in the page mode can be read out at 60ns cycle time per byte. The I/O pins serve as the ports for address and
data input/output as well as command input. This interface allows a reduced pin count and easy migration towards dif-
ferent densities, without any rearrangement of footprint.
Commands, Data and Addresses are synchronously introduced using CE#, WE#, ALE and CLE input pin.
The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where
required, and internal verification and margining of data.
The modifying can be locked using the WP# input pin.
The output pin RB# (open drain buffer) signals the status of the device during each operation. In a system with mul-
tiple memories the RB# pins can be connected all together to provide a global status signal.
Even the write-intensive systems can take advantage of the HY27(U/S)G(08/16)2G2M extended reliability of 100K pro-
gram/erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm.
Optionally the chip could be offered with the CE# don’t care function. This option allows the direct download of the
code from the NAND Flash memory device by a microcontroller, since the CE# transitions do not stop the read opera-
tion.
The copy back function allows the optimization of defective blocks management: when a page program operation fails
the data can be directly programmed in another page inside the same array section without the time consuming serial
data insertion phase.
The cache program feature allows the data insertion in the cache register while the data register is copied into the
flash array. This pipelined program operation improves the program throughput when long files are written inside the
memory.
A cache read feature is also implemented. This feature allows to dramatically improve the read throughput when con-
secutive pages have to be streamed out.
This device includes also extra features like OTP/Unique ID area, Automatic Read at Power Up, Read ID2 extension.
The HYNIX HY27(U/S)G(08/16)2G2M series is available in 48 - TSOP1 12 x 20 mm , 48 - USOP1 12 x 17 mm.
1.1 Product List
PART NUMBER
HY27SG082G2M
HY27SG162G2M
HY27UG082G2M
HY27UG162G2M
ORIZATION
x8
x16
x8
x16
VCC RANGE
1.70 - 1.95 Volt
48TSOP1 / 48USOP1
2.7V - 3.6 Volt
PACKAGE
Rev 0.7 / Nov. 2005
5
stm32/stm8
