HY29F040A Series
512K x 8-bit CMOS 5.0 volt-only, Sector Erase Flash Memory
KEY FEATURES
·
5.0 V ± 10% Read, Program, and Erase
- Minimizes system-level power requirements
·
High performance
-
55 ns access time
·
Compatible with JEDEC-Standard Commands
- Uses software commands, pinouts, and
packages following industry standards for
single power supply Flash memory
·
Minimum 100,000 Program/Erase Cycles
·
Sector Erase Architecture
- Eight equal size sectors of 64K bytes each
- Any combination of sectors can be erased
concurrently; also supports full chip erase
·
Erase Suspend/Resume
- Suspend a sector erase operation to allow a
data read or programming in a sector not
being erased within the same device
·
Internal Erase Algorithms
- Automatically erases a sector, any combination
of sectors, or the entire chip
·
Internal Programming Algorithms
- Automatically programs and verifies data at a
specified address.
·
Low Power Consumption
- 40 mA maximum active read current
- 60 mA maximum program/erase current
- 5
mA
maximum standby current
·
Sector Protection
- Hardware method disables any combination
of sectors from a program or erase operation
DESCRIPTION
The HY29F040A is a 4 Megabit, 5.0 volt-only CMOS
Flash memory device organized as a 512K bytes
of 8 bits each. The device is offered in standard
32-pin PDIP, 32-pin PLCC and 32-pin TSOP pack-
ages. It is designed to be programmed and
erased in-system with a 5.0 volt power-supply and
can also be reprogrammed in standard PROM
programmers.
The HY29F040A offers access times of 55 ns, 70
ns, 90 ns, 120 ns and 150 ns. The device has sepa-
rate chip enable (/CE), write enable (/WE) and out-
put enable (/OE) controls. Hyundai Flash memory
devices reliably store memory data even after
100,000 program/erase cycles.
The HY29F040A is entirely pin and command set
compatible with the JEDEC standard for 4 Mega-
bit Flash memory devices. The commands are writ-
ten to the command register using standard micropro-
cessor write timings. Register contents serve as
input to an internal state-machine which controls
the erase and programming circuitry. Write cycles
also internally latch addresses and data needed
for the programming and erase operations.
The HY29F040A is programmed by executing the
program command sequence. This will start the
internal byte programming algorithm that
automatically times the program pulse width and
also verifies the proper cell margin. Erase is
accomplished by executing either sector erase or
chip erase command sequence. This will start the
internal erasing algorithm that automatically times
the erase pulse width and also verifies the proper
cell margin. No preprogramming is required prior to
execution of the internal erase algorithm. Sectors
of the HY29F040A Flash memory array are electri-
cally erased via Fowler-Nordheim tunneling. Bytes
are programmed one byte at a time using a hot
electron injection mechanism.
The HY29F040A features a sector erase architecture.
The device memory array is divided into 8 sectors of
64K bytes each. The sectors can be erased indi-
vidually or in groups without affecting the data in
other sectors. The multiple sector erase and full
chip erase capabilities add flexibility to altering the
data in the device. To protect data in the device
from accidental program and erase, the device
also has a sector protect function. This function
hardware write protects the selected sectors. The sector
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licences are implied.
Rev.03/Aug.97
Hyundai Semiconductor
protect and sector unprotect features can be en-
abled in a PROM programmer.
The HY29F040A needs a single 5.0 volt power-
supply for read, program and erase operation. In-
ternally generated and well regulated voltages are
provided for program and erase operation. A low
Vcc detector inhibits write operations on loss of
power. End of program or erase is detected by /Data
Polling of DQ7 or by the Toggle Bit feature on DQ6.
Once program or erase cycle is successfully com-
pleted, the device internally resets to the Read
mode.
BLOCK DIAGRAM
DQ 0-DQ7
Vcc
Vss
State
C ontrol
WE
Com mand
R egister
P G M V oltage
G en erato r
Chip E nable
O u tput E nable
Log ic
E rase V oltage
G en erato r
Input/O utpu t
B uffers
CE
OE
STB
Data Latch
STB
Y-D ecoder
V cc D etector
A 0-A18
A ddress
Latch
Y -G ating
Tim e r
Cell M atrix
X-D ecoder
2
HY29F040A
PIN DESCRIPTION
Pin Name
A0 - A18
DQ0 - DQ7
/CE
/OE
/WE
Vss
Vcc
Pin Function
Address Inputs
Data Input/Output
Chip Enable
Output Enable
Write Enable
Device Ground
Device Power Supply
(5.0V
±
10 % for -70, -90, -120 and -150)
(5.0V
±
5 % for -55)
PIN CONNECTION
A1 1
A9
A8
A1 3
A1 4
A1 7
WE
V cc
A1 8
A1 6
A1 5
A1 2
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A1 0
CE
DQ 7
DQ 6
DQ 5
DQ 4
DQ 3
V ss
DQ 2
DQ 1
DQ 0
A0
A1
A2
A3
OE
A1 0
CE
DQ 7
DQ 6
DQ 5
DQ 4
DQ 3
V ss
DQ 2
DQ 1
DQ 0
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
32
31
31
30
30
29
29
28
28
27
27
26
26
25
25
24
24
23
23
22
22
21
21
20
20
19
19
18
18
17
17
A1 1
A9
A8
A1 3
A1 4
A1 7
WE
V cc
A1 8
A1 6
A1 5
A1 2
A7
A6
A5
A4
Standard TSOP
Reverse TSOP
A1 2
A1 5
A1 6
A1 8
A1 7
30
29
28
27
26
25
24
23
22
21
14
15
16
17
18
19
20
V cc
32
A1 8
A1 6
A1 5
A1 2
A7
A6
A5
A4
A3
A2
A1
A0
DQ 0
DQ 1
DQ 2
V ss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V cc
WE
A1 4
A1 3
A8
A9
A1 1
OE
A1 0
CE
DQ 7
DQ 6
DQ 5
DQ 4
A7
A6
A5
A4
A3
A2
A1
A0
DQ 0
31
A1 7
4
3
2
1
WE
5
6
7
8
9
10
11
12
13
A1 4
A1 3
A8
A9
A1 1
OE
A1 0
CE
DQ 7
DQ 1
DQ 2
V ss
DQ 3
DQ 4
DQ 5
DQ 3
PDIP
HY29F040A
PLCC
3
DQ 6
BUS OPERATION
Table 1. Bus Operations
(1)
OPERATION
Electronic ID Manufacturer Code
(2)
Electronic ID Device Code
(2)
Read
(3)
Standby
Output Disable
Write
Enable Sector Protect
Verify Sector Protect
/CE
L
L
L
H
L
L
L
L
/OE
L
L
L
X
H
H
V
ID
L
/WE
H
H
H
X
H
L
L
H
A0
L
H
A0
X
X
A0
X
L
A1
L
L
A1
X
X
A1
X
H
A6
L
L
A6
X
X
A6
X
L
A9
V
ID
V
ID
A9
X
X
A9
V
ID
V
ID
I/O
Code
Code
D
OUT
High Z
High Z
D
IN(4)
X
Code
Notes:
1. L = V
IL
, H = V
IH
, X = Don’t Care. See DC Characteristics for voltage levels.
2. Manufacturer and device codes may also be accessed via a command register sequence. Refer to Table 4.
3. /WE can be V
IL
if /CE is V
IL
, /OE at V
IH
initiates the write operations.
4. Refer to Table 4 for valid D
IN
during a write operation.
Table 2. Sector Protection Verify Electronic ID Codes
Type
A18
A17
A16
A6
A1
A0
Code
HEX
ADH
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
Manufacture Code
HY29F040A
Device Code
Sector Protection
X
X
X
V
IL
V
IL
V
IL
V
IL
V
IL
V
IH
V
IL
V
IH
V
IL
1
0
1
0
1
1
0
1
X
X
X
A4H
01H
(1)
1
0
0
0
1
0
0
0
0
0
1
0
0
0
0
1
Sector Addresses
Notes:
1. Outputs 01H at protected sector addresses, and output 00H at unprotected sector addresses.
4
HY29F040A
Table 3. Sector Addresses
A18
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
0
0
0
0
1
1
1
1
A17
0
0
1
1
0
0
1
1
A16
0
1
0
1
0
1
0
1
Address Range
00000H - 0FFFFH
10000H - 1FFFFH
20000H - 2FFFFH
30000H - 3FFFFH
40000H - 4FFFFH
50000H - 5FFFFH
60000H - 6FFFFH
70000H - 7FFFFH
Electronic ID Mode
The Electronic ID mode allows the reading out of
a binary code from the device and will identify its
manufacturer and device type. This mode is in-
tended for use by programming equipment for the
purpose of automatically matching the device to be
programmed with its corresponding programming
algorithm. This mode is functional over the entire
temperature range of the device.
To activate this mode, the programming equipment
must force V
ID
(11.5V to 12.5V) on address pin
A9. Two identifier bytes may then be sequenced
from the device outputs by toggling address A0
from V
IL
to V
IH
. All addresses are don’t cares ex-
cept A0, A1, A6, and A9.
The manufacturer and device codes may also be
read via the command register, (i.e., when
HY29F040A is erased or programmed in a system
without access to high voltage on the A9 pin). The
command sequence is illustrated in Table 4 (refer
to Electronic ID Command section).
Byte 0 (A0=V
IL
) represents the manufacturer’s code
(Hyundai Electronics=ADH) and byte 1 (A0=V
IH
)
the device identifier code (HY29F040A=A4H).
These two bytes are given in Table 2. All identifi-
ers for manufacturer and devices will exhibit odd
parity with the MSB (DQ7) defined as the parity
bit. To permit reading of the proper device codes
when executing the Electronic ID, A1 must be V
IL
(see Table 2).
Read Mode
The HY29F040A has three control functions which
must be satisfied to obtain data at the outputs. /
CE is the power control and should be used for
device selection. /OE is the output control and
should be used to gate data to the output pins if a
device is selected. As shown in Table 1, /WE
should be held at V
IH
, except in Write mode and
Enable Sector Protect mode.
Address access time (t
ACC
) is equal to the delay
from stable addresses to valid output data. The
chip enable access time (t
CE
) is the delay from
stable addresses and stable /CE to valid data at
the output pins. The output enable access time is
the delay from the falling edge of /OE to valid data
at the output pins (assuming the addresses have
been stable for at least t
ACC
-t
OE
time).
Standby Mode
The HY29F040A has two standby modes: a CMOS
standby mode (/CE input held at Vcc ± 0.5V), when
current consumed is typically less than 1
mA;
and a
TTL standby mode (/CE is held at V
IH
) when the
typical current required is reduced to 1 mA. In
standby mode, outputs are in a high impedance
state, independent of /OE input.
If the device is deselected during programming or
erase, the device will draw active current until the
programming or erase operation is completed.
HY29F040A
5
