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HY57Y281620HCLT-P

Synchronous DRAM, 8MX16, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54

器件类别：存储    存储   

厂商名称：SK Hynix(海力士)

厂商官网：http://www.hynix.com/eng/

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参数 预览 参数对比
器件参数
参数名称
属性值
零件包装代码
TSOP2
包装说明
TSOP2, TSOP54,.46,32
针数
54
Reach Compliance Code
compliant
ECCN代码
EAR99
访问模式
FOUR BANK PAGE BURST
最长访问时间
6 ns
其他特性
AUTO/SELF REFRESH
最大时钟频率 (fCLK)
100 MHz
I/O 类型
COMMON
交错的突发长度
1,2,4,8
JESD-30 代码
R-PDSO-G54
JESD-609代码
e6
长度
22.22 mm
内存密度
134217728 bit
内存集成电路类型
SYNCHRONOUS DRAM
内存宽度
16
功能数量
1
端口数量
1
端子数量
54
字数
8388608 words
字数代码
8000000
工作模式
SYNCHRONOUS
最高工作温度
70 °C
最低工作温度
组织
8MX16
输出特性
3-STATE
封装主体材料
PLASTIC/EPOXY
封装代码
TSOP2
封装等效代码
TSOP54,.46,32
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE, THIN PROFILE
电源
3 V
认证状态
Not Qualified
刷新周期
4096
座面最大高度
1.2 mm
自我刷新
YES
连续突发长度
1,2,4,8,FP
最大待机电流
0.001 A
最大压摆率
0.2 mA
最大供电电压 (Vsup)
3.3 V
最小供电电压 (Vsup)
2.7 V
标称供电电压 (Vsup)
3 V
表面贴装
YES
技术
CMOS
温度等级
COMMERCIAL
端子面层
TIN BISMUTH
端子形式
GULL WING
端子节距
0.8 mm
端子位置
DUAL
宽度
10.16 mm
Base Number Matches
1
文档预览
HY57Y281620HC(L)T
4 Banks x 2M x 16bits Synchronous DRAM
DESCRIPTION
The Hynix HY57Y281620HC(L)T is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications
which require large memory density and high bandwidth. HY57Y281620HC(L)T is organized as 4banks of 2,097,152x16
HY57Y281620HC(L)T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are
synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input
and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated
by a single control command (Burst length of 1,2,4,8, or full page), and the burst count sequence(sequential or interleave). A burst of
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
•
•
•
Single 3.0±0.3V power supply
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin
pitch
All inputs and outputs referenced to positive edge of system
clock
Data mask function by UDQM or LDQM
Internal four banks operation
•
•
•
•
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
•
- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS Latency ; 2, 3 Clocks
•
•
ORDERING INFORMATION
Part No.
HY57Y281620HCT-H
HY57Y281620HCT-P
HY57Y281620HCT-S
HY57Y281620HCLT-H
HY57Y281620HCLT-P
HY57Y281620HCLT-S
Clock Frequency
133MHz
100MHz
100MHz
133MHz
100MHz
100MHz
Power
Organization
Interface
Package
Normal
4Banks x 2Mbits
x16
Low power
LVTTL
400mil 54pin TSOP II
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.1/Apr. 02
2
HY57Y281620HC(L)T
PIN CONFIGURATION
V
DD
DQ0
V
DDQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
DDQ
DQ5
DQ6
V
SSQ
DQ7
V
DD
LDQM
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ15
V
SSQ
DQ14
DQ13
V
DDQ
DQ12
DQ11
V
SSQ
DQ10
DQ9
V
DDQ
DQ8
V
SS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
54pin TSOP II
400mil x 875mil
0.8mm pin pitch
PIN DESCRIPTION
PIN
CLK
CKE
CS
BA0, BA1
A0 ~ A11
Clock
Clock Enable
Chip Select
Bank Address
Address
Row Address Strobe, Col-
umn Address Strobe, Write
Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
No Connection
PIN NAME
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on
the rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will be
one of the states among power down, suspend or self refresh
Enables or disables all inputs except CLK, CKE, UDQM and LDQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8
Auto-precharge flag : A10
RAS, CAS and WE define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in write mode
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection
RAS, CAS, WE
UDQM, LDQM
DQ0 ~ DQ15
V
DD
/V
SS
V
DDQ
/V
SSQ
NC
Rev. 0.1/Apr. 02
3
HY57Y281620HC(L)T
FUNCTIONAL BLOCK DIAGRAM
2Mbit x 4banks x 16 I/O Synchronous DRAM
Self refresh logic
& timer
Internal Row
counter
CLK
Row active
2Mx16 Bank 3
Row
Pre
Decoders
2Mx16 Bank 2
X decoders
X decoders
2Mx16 Bank 1
2Mx16 Bank 0
X decoders
DQ0
DQ1
I/O Buffer & Logic
Sense AMP & I/O Gate
CKE
CS
RAS
CAS
WE
UDQM
LDQM
State Machine
Address buffers
X decoders
refresh
Column
Active
Memory
Cell
Array
Column
Pre
Decoders
Y decoders
DQ14
DQ15
Bank Select
Column Add
Counter
A0
A1
Address
Registers
Burst
Counter
A11
BA0
BA1
Mode Registers
CAS Latency
Data Out Control
Pipe Line Control
Rev. 0.1/Apr. 02
4
HY57Y281620HC(L)T
ABSOLUTE MAXIMUM RATINGS
Parameter
Ambient Temperature
Storage Temperature
Voltage on Any Pin relative to V
SS
Voltage on V
DD
relative to V
SS
Short Circuit Output Current
Power Dissipation
Soldering Temperature
⋅
Time
T
A
T
STG
V
IN
, V
OUT
V
DD,
V
DDQ
I
OS
P
D
T
SOLDER
Symbol
0 ~ 70
-55 ~ 125
-1.0 ~ 4.6
-1.0 ~ 4.6
50
1
260
⋅
10
Rating
°C
°C
V
V
mA
W
°C ⋅
Sec
Unit
Note :
Operation at above absolute maximum rating can adversely affect device reliability.
DC OPERATING CONDITION
(T
A
=0 to 70°C)
Parameter
Power Supply Voltage
Input High voltage
Input Low voltage
Symbol
V
DD
, V
DDQ
V
IH
V
IL
Min
2.7
2.0
-0.3
Typ
3.0
3.0
0
Max
3.3
V
DDQ
+ 0.3
0.8
Unit
V
V
V
Note
1
1,2
1,3
Note :
1.All voltages are referenced to V
SS
= 0V
2.V
IH
(max) is acceptable 5.6V AC pulse width with <=3ns of duration.
3.V
IL
(min) is acceptable -2.0V AC pulse width with <=3ns of duration.
AC OPERATING TEST CONDITION
(T
A
=0 to 70°C, V
DD
=3.0
±
0.3V, V
SS
=0V)
Parameter
AC Input High / Low Level Voltage
Input Timing Measurement Reference Level Voltage
Input Rise / Fall Time
Output Timing Measurement Reference Level Voltage
Output Load Capacitance for Access Time Measure-
ment
Symbol
V
IH
/ V
IL
Vtrip
tR / tF
Voutref
C
L
Value
2.4/0.4
1.4
1
1.4
50
Unit
V
V
ns
V
pF
1
Note
Note :
1.Output load to measure access times is equivalent to two TTL gates and one capacitor (50pF). For details, refer to AC/DC output
load circuit
Rev. 0.1/Apr. 02
5
HY57Y281620HC(L)T
CAPACITANCE
(TA=25°C, f=1MHz)
-H
Parameter
Pin
Symbol
Min
Input capacitance
CLK
A0 ~ A11, BA0, BA1, CKE, CS, RAS,
CAS, WE, UDQM, LDQM
Data input / output capacitance
DQ0 ~ DQ15
C
I1
CI
2
C
I/O
2.5
2.5
4.0
-P/S
Unit
Max
3.5
3.8
6.5
Min
2.5
2.5
4.0
Max
4.0
5.0
6.5
pF
pF
pF
OUTPUT LOAD CIRCUIT
Vtt=1.4V
RT=250
Ω
Output
Output
50pF
50pF
DC Output Load Circuit
AC Output Load Circuit
DC CHARACTERISTICS I
(TA=0 to 70°C, V
DD
=3.0
±
0.3V)
Parameter
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
I
LI
I
LO
V
OH
V
OL
Symbol
Min.
-1
-1
2.4
-
Max
1
1
-
0.4
Unit
uA
uA
V
V
Note
1
2
I
OH
= -2mA
I
OL
= +2mA
Note :
1.V
IN
= 0 to 3.3V, All other pins are not tested under V
IN
=0V
2.D
OUT
is disabled, V
OUT
=0 to 3.3
Rev. 0.1/Apr. 02
6
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参数对比
与HY57Y281620HCLT-P相近的元器件有：HY57Y281620HCT-P、HY57Y281620HCT-S、HY57Y281620HCLT-S、HY57Y281620HCT-H。描述及对比如下：
型号 HY57Y281620HCLT-P HY57Y281620HCT-P HY57Y281620HCT-S HY57Y281620HCLT-S HY57Y281620HCT-H
描述 Synchronous DRAM, 8MX16, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54 Synchronous DRAM, 8MX16, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54 Synchronous DRAM, 8MX16, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54 Synchronous DRAM, 8MX16, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54 Synchronous DRAM, 8MX16, 5.4ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
零件包装代码 TSOP2 TSOP2 TSOP2 TSOP2 TSOP2
包装说明 TSOP2, TSOP54,.46,32 TSOP2, TSOP54,.46,32 TSOP2, TSOP54,.46,32 TSOP2, TSOP54,.46,32 TSOP2, TSOP54,.46,32
针数 54 54 54 54 54
Reach Compliance Code compliant compliant compliant compliant compli
ECCN代码 EAR99 EAR99 EAR99 EAR99 EAR99
访问模式 FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST
最长访问时间 6 ns 6 ns 6 ns 6 ns 5.4 ns
其他特性 AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH
最大时钟频率 (fCLK) 100 MHz 100 MHz 100 MHz 100 MHz 133 MHz
I/O 类型 COMMON COMMON COMMON COMMON COMMON
交错的突发长度 1,2,4,8 1,2,4,8 1,2,4,8 1,2,4,8 1,2,4,8
JESD-30 代码 R-PDSO-G54 R-PDSO-G54 R-PDSO-G54 R-PDSO-G54 R-PDSO-G54
JESD-609代码 e6 e6 e6 e6 e6
长度 22.22 mm 22.22 mm 22.22 mm 22.22 mm 22.22 mm
内存密度 134217728 bit 134217728 bit 134217728 bit 134217728 bit 134217728 bi
内存集成电路类型 SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM
内存宽度 16 16 16 16 16
功能数量 1 1 1 1 1
端口数量 1 1 1 1 1
端子数量 54 54 54 54 54
字数 8388608 words 8388608 words 8388608 words 8388608 words 8388608 words
字数代码 8000000 8000000 8000000 8000000 8000000
工作模式 SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
最高工作温度 70 °C 70 °C 70 °C 70 °C 70 °C
组织 8MX16 8MX16 8MX16 8MX16 8MX16
输出特性 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 TSOP2 TSOP2 TSOP2 TSOP2 TSOP2
封装等效代码 TSOP54,.46,32 TSOP54,.46,32 TSOP54,.46,32 TSOP54,.46,32 TSOP54,.46,32
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE
电源 3 V 3 V 3 V 3 V 3 V
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
刷新周期 4096 4096 4096 4096 4096
座面最大高度 1.2 mm 1.2 mm 1.2 mm 1.2 mm 1.2 mm
自我刷新 YES YES YES YES YES
连续突发长度 1,2,4,8,FP 1,2,4,8,FP 1,2,4,8,FP 1,2,4,8,FP 1,2,4,8,FP
最大待机电流 0.001 A 0.001 A 0.001 A 0.001 A 0.001 A
最大压摆率 0.2 mA 0.2 mA 0.2 mA 0.2 mA 0.22 mA
最大供电电压 (Vsup) 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
最小供电电压 (Vsup) 2.7 V 2.7 V 2.7 V 2.7 V 2.7 V
标称供电电压 (Vsup) 3 V 3 V 3 V 3 V 3 V
表面贴装 YES YES YES YES YES
技术 CMOS CMOS CMOS CMOS CMOS
温度等级 COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
端子面层 TIN BISMUTH TIN BISMUTH TIN BISMUTH TIN BISMUTH TIN BISMUTH
端子形式 GULL WING GULL WING GULL WING GULL WING GULL WING
端子节距 0.8 mm 0.8 mm 0.8 mm 0.8 mm 0.8 mm
端子位置 DUAL DUAL DUAL DUAL DUAL
宽度 10.16 mm 10.16 mm 10.16 mm 10.16 mm 10.16 mm
厂商名称 - SK Hynix(海力士) SK Hynix(海力士) SK Hynix(海力士) SK Hynix(海力士)
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器件捷径:
E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ
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