HY5DU12422B(L)F
HY5DU12822B(L)F
HY5DU121622B(L)F
512Mb DDR SDRAM
HY5DU12422B(L)F
HY5DU12822B(L)F
HY5DU121622B(L)F
This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.1 / Aug. 2003
1
HY5DU12422B(L)F
HY5DU12822B(L)F
HY5DU121622B(L)F
Revision History
Revision No.
0.1
History
Unitial Draft
Draft Date
Aug.2003
Remark
Rev. 0.1 / Aug. 2003
2
HY5DU12422B(L)F
HY5DU12822B(L)F
HY5DU121622B(L)F
DESCRIPTION
Preliminary
The HY5DU12422B(L)F, HY5DU12822B(L)F and HY5DU121622B(L)F are a 536,870,912-bit CMOS Double Data
Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density
and high bandwidth.
This Hynix 512Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
•
•
•
•
•
•
•
V
DD
, V
DDQ
= 2.6V +/- 0.1V
All inputs and outputs are compatible with SSTL_2
interface
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous - data transaction aligned to
bidirectional data strobe (DQS)
x16 device has two bytewide data strobes (UDQS,
LDQS) per each x8 I/O
Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
On chip DLL align DQ and DQS transition with CK
transition
DM mask write data-in at the both rising and falling
edges of the data strobe
•
All addresses and control inputs except data, data
strobes and data masks latched on the rising edges
of the clock
Programmable /CAS latency 3 supported
Programmable burst length 2 / 4 / 8 with both
sequential and interleave mode
Internal four bank operations with single pulsed
/RAS
Auto refresh and self refresh supported
tRAS lock out function supported
8192 refresh cycles / 64ms
60 Ball FBGA Package Type
Full and Half strength driver option controlled by
EMRS
•
•
•
•
•
•
•
•
•
•
ORDERING INFORMATION
Part No.
HY5DU12422B(L)F-X*
HY5DU12822B(L)F-X*
HY5DU121622B(L)F-X*
OPERATING FREQUENCY
Package
60 Ball
FBGA
Configuration
128Mx4
64Mx8
32Mx16
Grade
- D4
- D43
CL3
200MHz
200MHz
Remark
(CL-tRCD-tRP)
DDR400 (3-4-4)
DDR400 (3-3-3)
* Note : D of speed indicates DDR400.
Rev. 0.1 / Aug. 2003
3
HY5DU12422B(L)F
HY5DU12822B(L)F
HY5DU121622B(L)F
PIN CONFIGURATION
9
VDDQ
NC
NC
NC
NC
NC
VSSQ
NC
VSS
A
VDD
NC
VDDQ
VSSQ
DQ7
VSS
A
VDD
NC
NC
VDDQ
DQ3
B
DQ0
VSSQ
NC
NC
VDDQ
DQ6
B
DQ0
VSSQ
NC
VSSQ
NC
C
NC
VDDQ
NC
NC
VSSQ
DQ5
C
DQ2
VDDQ
NC
VDDQ
DQ2
D
DQ1
VSSQ
NC
NC
VDDQ
DQ4
D
DQ3
VSSQ
NC
VSSQ
DQS
E
NC
VDDQ
NC
NC
VSSQ
DQS
E
NC
VDDQ
VREF
VSS
DM
F
NC
VDD
NC
VREF
VSS
DM
F
NC
VDD
CK
CK
G
WE
CAS
CK
CK
G
WE
CAS
A12
CKE
H
RAS
CS
A12
CKE
H
RAS
CS
A11
A9
J
BA1
BA0
A11
A9
J
BA1
BA0
A8
A7
K
A0
A10/AP
A8
A7
K
A0
A10/AP
A6
A5
L
A2
A1
A6
A5
L
A2
A1
A4
VSS
M
VDD
A3
A4
VSS
M
VDD
A3
x4 Device Ball Pattern
9
8
x8 Device Ball Pattern
: Ball Existing
: Depopulated Ball
[ For Reference Only ]
(X16)
1
2
3
7
VSSQ
DQ15
VSS
A
VDD
NC
VDDQ
Top View (See the balls through the Package)
DQ14
VDDQ
DQ13
B
DQ2
VSSQ
DQ1
1
DQ12
2
3
4
5
6
7
8
9
VSSQ
DQ11
C
DQ4
VDDQ
DQ3
A
DQ6
DQ10
VDDQ
DQ9
D
VSSQ
DQ5
B
C
1.0mm
DQ8
VSSQ
UDQS
E
LDQS
VDDQ
DQ7
D
E
VREF
VSS
UDM
F
LDM
VDD
A13, NC
F
WE
CK
CK
G
CAS
G
H
13.0mm
A12, NC
CKE
H
RAS
CS
J
K
L
A11
A9
J
BA1
BA0
A8
A7
K
A0
A10/AP
M
A6
A5
L
A2
A1
0.8mm
8.0mm
A4
VSS
M
VDD
A3
x16 Device Ball Pattern
BGA Package Ball Pattern
Top View
ROW AND COLUMN ADDRESS TABLE
ITEMS
Organization
Row Address
Column Address
Bank Address
Auto Precharge Flag
Refresh
128Mx4
32M x 4 x 4banks
A0 - A12
A0-A9, A11, A12
BA0, BA1
A10
8K
64Mx8
16M x 8 x 4banks
A0 - A12
A0-A9, A11
BA0, BA1
A10
8K
32Mx16
8M x 16 x 4banks
A0 - A12
A0-A9
BA0, BA1
A10
8K
Rev. 0.1 / Aug. 2003
8
9
8
(X4)
1
2
3
7
(X8)
1
2
3
7
4
HY5DU12422B(L)F
HY5DU12822B(L)F
HY5DU121622B(L)F
PIN DESCRIPTION
PIN
CK, /CK
TYPE
Input
DESCRIPTION
Clock: CK and /CK are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of /CK. Output
(read) data is referenced to the crossings of CK and /CK (both directions of crossing).
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER
DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row
ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF
REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE
must be maintained high throughout READ and WRITE accesses. Input buffers, excluding
CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are
disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW
level after Vdd is applied.
Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com-
mands are masked when CS is registered high. CS provides for external bank selection on
systems with multiple banks. CS is considered part of the command code.
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRE-
CHARGE command is being applied.
Address Inputs: Provide the row address for ACTIVE commands, and the column address
and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A10 is sampled during a precharge command to
determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10
HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The
address inputs also provide the op code during a MODE REGISTER SET command. BA0
and BA1 define which mode register is loaded during the MODE REGISTER SET command
(MRS or EMRS).
Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being
entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH along with that input data during a WRITE access. DM is sampled
on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ
and DQS loading. For the x16, LDM corresponds to the data on DQ0-Q7; UDM corre-
sponds to the data on DQ8-Q15.
Data Strobe: Output with read data, input with write data. Edge aligned with read data,
centered in write data. Used to capture write data. For the x16, LDQS corresponds to the
data on DQ0-Q7; UDQS corresponds to the data on DQ8-Q15.
Data input / output pin : Data bus
Power supply for internal circuits and input buffers.
Power supply for output buffers for noise immunity.
Reference voltage for inputs for SSTL interface.
No connection.
CKE
Input
/CS
Input
BA0, BA1
Input
A0 ~ A12
Input
/RAS, /CAS, /WE
Input
DM
(LDM,UDM)
Input
DQS
(LDQS,UDQS)
DQ
V
DD
/V
SS
V
DDQ
/V
SSQ
V
REF
NC
I/O
I/O
Supply
Supply
Supply
NC
Rev. 0.1 / Aug. 2003
5
