HY5DU283222AF(P)
128M(4Mx32) GDDR SDRAM
HY5DU283222AF(P)
This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any respon-
sibility for use of circuits described. No patent licenses are implied.
Rev. 0.8/ Jun. 2004
1
HY5DU283222AF(P)
Revision History
Revision
No.
0.1
0.11
0.2
0.3
Defined target spec.
500MHz speed bin added
Defined IDD specification
1) Added 222MHz with CL3 and tCK_max=10ns at HY5DU283222AF-36
2) Changed VDD_min value of HY5DU283222AF-36 from 2.375V to 2.2V
3) Changed AC parameters value of HY5DU283222AF-28/33
- tRCDRD/tRP : from 6 tCK to 5 tCK
- tDAL : from 9 tCK to 8 tCK
- tRFC : from 19 tCK to 17 tCK
4) Changed IDD2N target specification
5) Changed tCK_max value of HY5DU283222AF-33/36 from 6ns to 10ns
Added Pb free part at HY5DU283222AF-33/36
Changed CAS Latency of HY5DU283222AF-28 from CL5 to CL4
Changed tRAS_max Value from 120K to 100K in All Frequency
Insert Overshoot/ Under Specification
Insert tDSS/ tDSH parameter
Added 250MHz/ 200MHz speed bin
History
Draft Date
Nov. 2002
Dec. 2002
Feb. 2003
Mar. 2003
Remark
0.4
0.5
0.6
0.7
0.8
Apr. 2003
June 2003
Aug. 2003
Sep. 2003
Jun. 2004
Rev. 0.8 / Jun. 2004
2
HY5DU283222AF(P)
DESCRIPTION
The Hynix HY5DU283222 is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the
point-to-point applications which requires high bandwidth.
The Hynix 4Mx32 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
•
•
•
•
•
•
•
•
2.5V +/- 5% V
DD
and V
DDQ
power supply
supports 300/275/250/200MHz
2.8V +/- 5% V
DD
and V
DDQ
power supply
supports 500/450/400/350MHz
All inputs and outputs are compatible with SSTL_2
interface
12mm x 12mm, 144ball FBGA with 0.8mm pin pitch
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous - data transaction aligned to
bidirectional data strobe (DQS0 ~ DQS3)
Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
•
•
•
•
•
•
•
Data(DQ) and Write masks(DM) latched on the both
rising and falling edges of the data strobe
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
Write mask byte controls by DM (DM0 ~ DM3)
Programmable /CAS Latency 5, 4 and 3 supported
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
Internal 4 bank operations with single pulsed /RAS
tRAS Lock-Out function supported
Auto refresh and self refresh supported
4096 refresh cycles / 32ms
Half strength and Matched Impedance driver option
controlled by EMRS
•
•
•
ORDERING INFORMATION
Part No.
HY5DU283222AF-2
HY5DU283222AF-22
HY5DU283222AF-25
HY5DU283222AF-28
HY5DU283222AF(P)-33
HY5DU283222AF(P)-36
HY5DU283222AF(P)-4
HY5DU283222AF(P)-5
V
DD
2.5V
V
DDQ
2.5V
V
DD
2.8V
V
DDQ
2.8V
Power
Supply
Clock
Frequency
500MHz
450MHz
400MHz
350MHz
300MHz
275MHz
250MHz
200MHz
Max Data Rate
1000Mbps/pin
900Mbps/pin
800Mbps/pin
700Mbps/pin
600Mbps/pin
550Mbps/pin
500Mbps/pin
400Mbps/pin
SSTL_2
12mm x 12mm
144Ball FBGA
interface
Package
Note)
Hynix supports Pb free parts for each speed grade with same specification, except Pb free material.
We’ll add “P” character after “F” for Pb Free product. For example, the part number of 300MHz Pb Free
product is HY5DU283222AFP-33.
Rev. 0.8 / Jun. 2004
3
HY5DU283222AF(P)
PIN CONFIGURATION
(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
B
DQS0
DM0
VSSQ
DQ3
DQ2
DQ0
DQ31
DQ29
DQ28
VSSQ
DM3
DQS3
C
DQ4
VDDQ
NC
VDDQ
DQ1
VDDQ
VDDQ
DQ30
VDDQ
NC
VDDQ
DQ27
D
DQ6
DQ5
VSSQ
VSSQ
VSSQ
VDD
VDD
VSSQ
VSSQ
VSSQ
DQ26
DQ25
E
DQ7
VDDQ
VDD
VSS
VSSQ
VSS
VSS
VSSQ
VSS
VDD
VDDQ
DQ24
F
DQ17
DQ16
VDDQ
VSSQ
VSS
Termal
VSS
Termal
VSS
Termal
VSS
Termal
VSSQ
VDDQ
DQ15
DQ14
G
DQ19
DQ18
VDDQ
VSSQ
VSS
Termal
VSS
Termal
VSS
Termal
VSS
Termal
VSSQ
VDDQ
DQ13
DQ12
H
DQS2
DM2
NC
VSSQ
VSS
Termal
VSS
Termal
VSS
Termal
VSS
Termal
VSSQ
NC
DM1
DQS1
J
DQ21
DQ20
VDDQ
VSSQ
VSS
Termal
VSS
Termal
VSS
Termal
VSS
Termal
VSSQ
VDDQ
DQ11
DQ10
K
DQ22
DQ23
VDDQ
VSSQ
VSS
VSS
VSS
VSS
VSSQ
VDDQ
DQ9
DQ8
L
/CAS
/WE
VDD
VSS
A10
VDD
VDD
NC2
VSS
VDD
NC
NC
M
/RAS
NC
NC
BA1
A2
A11
A9
A5
NC3
CLK
/CLK
NC
N
/CS
NC
BA0
A0
A1
A3
A4
A6
A7
A8/AP
CKE
VREF
P
Note :
1. Outer ball, A1~A14, P1~P14, A1~P1, A14~P14 are depopulated.
2. Ball L9(NC2) is reserved for A12.
3. Ball M10(NC3) is reserved for BA2.
ROW and COLUMN ADDRESS TABLE
Items
Organization
Row Address
Column Address
Bank Address
Auto Precharge Flag
Refresh
4Mx32
1M x 32 x 4banks
A0 ~ A11
A0 ~ A7
BA0, BA1
A8
4K
Rev. 0.8 / Jun. 2004
4
HY5DU283222AF(P)
PIN DESCRIPTION
PIN
CK, /CK
TYPE
Input
DESCRIPTION
Clock: CK and /CK are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of /CK. Output
(read) data is referenced to the crossings of CK and /CK (both directions of crossing).
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER
DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row
ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF
REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE
must be maintained high throughout READ and WRITE accesses. Input buffers, excluding
CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are
disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW
level after Vdd is applied.
Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com-
mands are masked when CS is registered high. CS provides for external bank selection on
systems with multiple banks. CS is considered part of the command code.
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRE-
CHARGE command is being applied.
Address Inputs: Provide the row address for ACTIVE commands, and the column address
and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A8 is sampled during a precharge command to
determine whether the PRECHARGE applies to one bank (A8 LOW) or all banks (A8
HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The
address inputs also provide the op code during a MODE REGISTER SET command. BA0
and BA1 define which mode register is loaded during the MODE REGISTER SET command
(MRS or EMRS).
Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being
entered.
Input Data Mask: DM(0~3) is an input mask signal for write data. Input data is masked
when DM is sampled HIGH along with that input data during a WRITE access. DM is sam-
pled on both edges of DQS. Although DM pins are input only, the DM loading matches the
DQ and DQS loading. DM0 corresponds to the data on DQ0-Q7; DM1 corresponds to the
data on DQ8-Q15; DM2 corresponds to the data on DQ16-Q23; DM3 corresponds to the
data on DQ24-Q31.
Data Strobe: Output with read data, input with write data. Edge aligned with read data,
centered in write data. Used to capture write data. DQS0 corresponds to the data on
DQ0-Q7; DQS1 corresponds to the data on DQ8-Q15; DQS2 corresponds to the data on
DQ16-Q23; DQS3 corresponds to the data on DQ24-Q31
Data input / output pin : Data Bus
Power supply for internal circuits and input buffers.
Power supply for output buffers for noise immunity.
Reference voltage for inputs for SSTL interface.
No connection.
CKE
Input
/CS
Input
BA0, BA1
Input
A0 ~ A11
Input
/RAS, /CAS, /WE
Input
DM0 ~ DM3
Input
DQS0 ~ DQS3
I/O
DQ0 ~ DQ31
V
DD
/V
SS
V
DDQ
/V
SSQ
V
REF
NC
I/O
Supply
Supply
Supply
NC
Rev. 0.8 / Jun. 2004
5
