256Mb DDR SDRAM
HY5DU56822E(L)TP-xI
HY5DU561622E(L)TP-xI
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.1 /June. 2006
1
HY5DU56822E(L)TP-xI
HY5DU561622E(L)TP-xI
1
Revision History
Revision No.
1.0
1.1
First release
Added CL2 & CL2.5 values to the DDR400B in the AC CHARACTERISTICS
History
Draft Date
Apr. 2006
June 2006
Remark
Rev. 1.1 /June. 2006
2
HY5DU56822E(L)TP-xI
HY5DU561622E(L)TP-xI
1
DESCRIPTION
The HY5DU56822E(L)TP and HY5DU561622E(L)TP are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous
DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth.
This Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
•
•
•
•
•
•
•
V
DD
, V
DDQ
= 2.5V +/- 0.2V for DDR200, 266, 333
V
DD
, V
DDQ
= 2.6V +0.1V / -0.2V for DDR400
All inputs and outputs are compatible with SSTL_2
interface
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous - data transaction aligned to
bidirectional data strobe (DQS)
x16 device has two bytewide data strobes (UDQS,
LDQS) per each x8 I/O
Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
On chip DLL align DQ and DQS transition with CK
transition
DM mask write data-in at the both rising and falling
edges of the data strobe
•
•
•
•
•
•
•
•
•
All addresses and control inputs except data, data
strobes and data masks latched on the rising edges
of the clock
Programmable CAS latency 2/2.5 (DDR200, 266,
333) and 3 (DDR400) supported
Programmable burst length 2/4/8 with both sequen-
tial and interleave mode
Internal four bank operations with single pulsed
/RAS
Auto refresh and self refresh supported
tRAS lock out function supported
8192 refresh cycles/64ms
JEDEC standard 400mil 66pin TSOP-II with 0.65mm
pin pitch
Lead free (*ROHS Compliant)
Industrial temperature supported: -40 to 85
o
C
•
•
•
ORDERING INFORMATION
Part No.
HY5DU56822E(L)TP-x*I
HY5DU561622E(L)TP-x*I
Configuration
32Mx8
16Mx16
Package
400mil
TSOP-II
(Lead free)
OPERATING FREQUENCY
Grade
-D43
-J
-K
-H
-L
Clock Rate
200MHz@CL3
133MHz@CL2
133MHz@CL2
100MHz@CL2
166MHz@CL2.5
133MHz@CL2.5
133MHz@CL2.5
Remark
(CL-tRCD-tRP)
DDR400B (3-3-3)
DDR333 (2.5-3-3)
DDR266A (2-3-3)
DDR266B (2.5-3-3)
DDR200 (2-2-2)
* x means speed grade
*ROHS (Restriction Of Hazardous Substances)
100MHz@CL2
Rev. 1.1 /June. 2006
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HY5DU56822E(L)TP-xI
HY5DU561622E(L)TP-xI
1
PIN CONFIGURATION
x8
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
x16
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
x16
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
/CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
x8
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
400mil X 875mil
66pin TSOP -II
0.65mm pin pitch
(Lead free)
ROW AND COLUMN ADDRESS TABLE
ITEMS
Organization
Row Address
Column Address
Bank Address
Auto Precharge Flag
Refresh
32Mx8
8M x 8 x 4banks
A0 - A12
A0-A9
BA0, BA1
A10
8K
16Mx16
4M x 16 x 4banks
A0 - A12
A0-A8
BA0, BA1
A10
8K
Rev. 1.1 /June. 2006
4
HY5DU56822E(L)TP-xI
HY5DU561622E(L)TP-xI
1
PIN DESCRIPTION
PIN
TYPE
DESCRIPTION
Clock: CK and /CK are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of /CK. Output
(read) data is referenced to the crossings of CK and /CK (both directions of crossing).
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER
DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row
ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF
REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE
must be maintained high throughout READ and WRITE accesses. Input buffers, excluding
CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are dis-
abled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level
after VDD is applied.
Chip Select: Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com-
mands are masked when CS is registered high. CS provides for external bank selection on
systems with multiple banks. CS is considered part of the command code.
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRE-
CHARGE command is being applied.
Address Inputs: Provide the row address for ACTIVE commands, and the column address
and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A10 is sampled during a precharge command to
determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10
HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The
address inputs also provide the op code during a MODE REGISTER SET command. BA0 and
BA1 define which mode register is loaded during the MODE REGISTER SET command (MRS
or EMRS).
Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being
entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM
is sampled HIGH along with that input data during a WRITE access. DM is sampled on both
edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS
loading. For the x16, LDM corresponds to the data on DQ0-Q7; UDM corresponds to the
data on DQ8-Q15.
Data Strobe: Output with read data, input with write data. Edge aligned with read data,
centered in write data. Used to capture write data. For the x16, LDQS corresponds to the
data on DQ0-Q7; UDQS corresponds to the data on DQ8-Q15.
Data input / output pin: Data bus
Power supply for internal circuits and input buffers.
Power supply for output buffers for noise immunity.
Reference voltage for inputs for SSTL interface.
No connection.
CK, /CK
Input
CKE
Input
/CS
Input
BA0, BA1
Input
A0 ~ A12
Input
/RAS, /CAS, /WE
Input
DM
(LDM,UDM)
Input
DQS
(LDQS,UDQS)
DQ
V
DD
/V
SS
V
DDQ
/V
SSQ
V
REF
NC
I/O
I/O
Supply
Supply
Supply
NC
Rev. 1.1 /June. 2006
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