HY5PS12421C(L)FP
HY5PS12821C(L)FP
HY5PS121621C(L)FP
512Mb DDR2 SDRAM
HY5PS12421C(L)FP
HY5PS12821C(L)FP
HY5PS121621C(L)FP
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.8 / Oct. 2007
1
1HY5PS12421C(L)FP
1HY5PS12821C(L)FP
1HY5PS121621C(L)FP
Revision History
Rev.
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
History
Preliminary
IDD Spec. Changed
Removed improper note in ODT spec.
Updated IDD3P-S value/OCD Default Characteristics
Updated IDD spec for x8 org. on page 16
Removed Y4 Speed bin
Updated Timing Patterns (DDR2-800 5/5/5 and 6/6/6)
Corrected Typo
Draft Date
May 2006
July 2006
July 2006
Aug. 2006
Feb. 2007
July 2007
Sep. 2007
Oct. 2007
Rev. 0.8 / Oct. 2007
2
1HY5PS12421C(L)FP
1HY5PS12821C(L)FP
1HY5PS121621C(L)FP
Contents
1. Description
1.1 Device Features and Ordering Information
1.1.1 Key Features
1.1.2 Ordering Information
1.1.3 Ordering Frequency
1.2 Pin configuration
1.3 Pin Description
2. Maximum DC ratings
2.1 Absolute Maximum DC Ratings
2.2 Operating Temperature Condition
3. AC & DC Operating Conditions
3.1 DC Operating Conditions
5.1.1 Recommended DC Operating Conditions(SSTL_1.8)
5.1.2 ODT DC Electrical Characteristics
3.2 DC & AC Logic Input Levels
3.2.1 Input DC Logic Level
3.2.2 Input AC Logic Level
3.2.3 AC Input Test Conditions
3.2.4 Differential Input AC Logic Level
3.2.5 Differential AC output parameters
3.3 Output Buffer Levels
3.3.1 Output AC Test Conditions
3.3.2 Output DC Current Drive
3.3.3 OCD default characteristics
3.4 IDD Specifications & Measurement Conditions
3.5 Input/Output Capacitance
4. AC Timing Specifications
5. Package Dimensions
Rev. 0.8 / Oct. 2007
3
1HY5PS12421C(L)FP
1HY5PS12821C(L)FP
1HY5PS121621C(L)FP
1. Description
1.1 Device Features & Ordering Information
1.1.1 Key Features
• VDD ,VDDQ =1.8 +/- 0.1V
• All inputs and outputs are compatible with SSTL_18 interface
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)
• Differential Data Strobe (DQS, DQS)
• Data outputs on DQS, DQS edges when read (edged DQ)
• Data inputs on DQS centers when write(centered DQ)
• On chip DLL align DQ, DQS and DQS transition with CK transition
• DM mask write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
• Programmable CAS latency 3, 4, 5 and 6 supported
• Programmable additive latency 0, 1, 2, 3, 4 and 5 supported
• Programmable burst length 4 / 8 with both nibble sequential and interleave mode
• Internal four bank operations with single pulsed RAS
• Auto refresh and self refresh supported
• tRAS lockout supported
• 8K refresh cycles /64ms
• JEDEC standard 60ball FBGA(x4/x8) & 84ball FBGA(x16)
• Full strength driver option controlled by EMRS
• On Die Termination supported
• Off Chip Driver Impedance Adjustment supported
• Read Data Strobe supported (x8 only)
• Self-Refresh High Temperature Entry
• Partial Array Self Refresh support
Ordering Information
Part No.
Organization
Package
Operating Frequency
Speed Bin
E3
Lead free**
C4
Y5
S5
S6
tCK(ns)
5
3.75
3
2.5
2.5
CL
3
4
5
5
6
tRCD
3
4
5
5
6
tRP
3
4
5
5
6
Unit
Clk
Clk
Clk
Clk
Clk
HY5PS12421C(L)FP-X*
HY5PS12821C(L)FP-X*
HY5PS121621C(L)FP-X*
128Mx4
64Mx8
32Mx16
Note:
1. -X* is the speed bin, refer to the Operation Frequency table for
complete Part No.
2. Hynix Lead-free products are compliant to RoHS.
Rev. 0.8 / Oct. 2007
4
1HY5PS12421C(L)FP
1HY5PS12821C(L)FP
1HY5PS121621C(L)FP
1.2 Pin Configuration & Address Table
128Mx4 DDR2 Pin Configuration(Top view: see balls through package)
1
VDD
NC
VDDQ
NC
VDDL
2
NC
VSSQ
DQ1
VSSQ
VREF
CKE
3
VSS
DM
VDDQ
DQ3
VSS
WE
BA1
A1
A5
A9
NC
A
B
C
D
E
F
G
H
J
K
L
7
VSSQ
DQS
VDDQ
DQ2
VSSDL
RAS
CAS
A2
A6
A11
NC
8
DQS
VSSQ
DQ0
VSSQ
CK
CK
CS
A0
A4
A8
A13
9
VDDQ
NC
VDDQ
NC
VDD
ODT
NC
BA0
A10
VDD
VSS
A3
A7
VSS
VDD
A12
ROW AND COLUMN ADDRESS TABLE
ITEMS
# of Bank
Bank Address
Auto Precharge Flag
Row Address
Column Address
Page size
128Mx4
4
BA0, BA1
A10/AP
A0 - A13
A0-A9, A11
1 KB
Rev. 0.8 / Oct. 2007
5
